sdr_test.vo

sdram读写

// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 9.1 Build 222 10/21/2009 SJ Full Version"

// DATE "11/13/2010 16:15:14"

// 
// Device: Altera EP2C5Q208C8 Package PQFP208
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module sdr_test (
	clk,
	rst_n,
	sdram_clk,
	sdram_cke,
	sdram_cs_n,
	sdram_ras_n,
	sdram_cas_n,
	sdram_we_n,
	sdram_ba,
	sdram_addr,
	sdram_data,
	rs232_tx,
	sdram_ldqm,
	sdram_udqm,
	led,
	rdf_dout);
input 	clk;
input 	rst_n;
output 	sdram_clk;
output 	sdram_cke;
output 	sdram_cs_n;
output 	sdram_ras_n;
output 	sdram_cas_n;
output 	sdram_we_n;
output 	[1:0] sdram_ba;
output 	[11:0] sdram_addr;
inout 	[15:0] sdram_data;
output 	rs232_tx;
output 	sdram_ldqm;
output 	sdram_udqm;
output 	[3:0] led;
output 	[15:0] rdf_dout;

// Design Ports Information
// clk	=>  Location: PIN_23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// rst_n	=>  Location: PIN_24,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// sdram_clk	=>  Location: PIN_116,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_cke	=>  Location: PIN_117,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_cs_n	=>  Location: PIN_144,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_ras_n	=>  Location: PIN_143,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_cas_n	=>  Location: PIN_142,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_we_n	=>  Location: PIN_141,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_ba[0]	=>  Location: PIN_145,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_ba[1]	=>  Location: PIN_146,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[0]	=>  Location: PIN_149,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[1]	=>  Location: PIN_150,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[2]	=>  Location: PIN_151,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[3]	=>  Location: PIN_152,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[4]	=>  Location: PIN_137,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[5]	=>  Location: PIN_135,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[6]	=>  Location: PIN_134,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[7]	=>  Location: PIN_133,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[8]	=>  Location: PIN_128,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[9]	=>  Location: PIN_127,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[10]	=>  Location: PIN_147,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_addr[11]	=>  Location: PIN_118,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rs232_tx	=>  Location: PIN_37,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_ldqm	=>  Location: PIN_139,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_udqm	=>  Location: PIN_115,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// led[0]	=>  Location: PIN_31,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// led[1]	=>  Location: PIN_33,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// led[2]	=>  Location: PIN_34,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// led[3]	=>  Location: PIN_35,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[0]	=>  Location: PIN_193,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[1]	=>  Location: PIN_195,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[2]	=>  Location: PIN_75,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[3]	=>  Location: PIN_191,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[4]	=>  Location: PIN_187,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[5]	=>  Location: PIN_189,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[6]	=>  Location: PIN_12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[7]	=>  Location: PIN_13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[8]	=>  Location: PIN_72,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[9]	=>  Location: PIN_70,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[10]	=>  Location: PIN_198,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[11]	=>  Location: PIN_185,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[12]	=>  Location: PIN_188,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[13]	=>  Location: PIN_200,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[14]	=>  Location: PIN_192,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// rdf_dout[15]	=>  Location: PIN_181,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[0]	=>  Location: PIN_95,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[1]	=>  Location: PIN_96,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[2]	=>  Location: PIN_97,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[3]	=>  Location: PIN_99,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[4]	=>  Location: PIN_101,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[5]	=>  Location: PIN_102,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[6]	=>  Location: PIN_103,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[7]	=>  Location: PIN_104,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[8]	=>  Location: PIN_114,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[9]	=>  Location: PIN_113,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[10]	=>  Location: PIN_112,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[11]	=>  Location: PIN_110,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[12]	=>  Location: PIN_108,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[13]	=>  Location: PIN_107,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[14]	=>  Location: PIN_106,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA
// sdram_data[15]	=>  Location: PIN_105,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 24mA

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("sdr_test_v.sdo");
// synopsys translate_on

wire \uut_sdramtop|module_001|work_state_r.0100~regout ;
wire \uut_sdramtop|module_001|work_state_r.0011~regout ;
wire \uut_sdramtop|module_002|WideOr0~0_combout ;
wire \uut_sdramtop|module_002|Selector15~0_combout ;
wire \uut_sdramtop|module_002|Selector22~0_combout ;
wire \uut_sdramtop|module_002|Selector20~0_combout ;
wire \uut_sdramtop|module_002|Selector19~0_combout ;
wire \uut_uartctrl|uut_tx|Mux0~0_combout ;
wire \uut_uartctrl|uut_tx|Mux0~1_combout ;
wire \uut_led_test|Equal0~3_combout ;
wire \uut_led_test|Equal0~5_combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ;
wire \uut_sdramtop|module_001|Equal0~2_combout ;
wire \uut_sdramtop|module_001|Selector11~1_combout ;
wire \uut_sdramtop|module_001|Selector13~0_combout ;
wire \uut_sdramtop|module_001|Selector13~1_combout ;
wire \uut_sdramtop|module_001|work_state_r~24_combout ;
wire \uut_sdramtop|module_001|Selector14~0_combout ;
wire \uut_datagene|rd_addr[8]~27_combout ;
wire \uut_datagene|wr_addr[5]~21_combout ;
wire \uut_datagene|wr_addr[9]~29_combout ;
wire \uut_datagene|always3~1_combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|op_1~10_combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|op_1~14_combout ;
wire \uut_led_test|cnt[3]~28_combout ;
wire \uut_led_test|cnt[5]~32_combout ;
wire \uut_led_test|cnt[16]~54_combout ;
wire \uut_led_test|cnt[18]~58_combout ;
wire \uut_led_test|cnt[19]~60_combout ;
wire \uut_led_test|cnt[21]~64_combout ;
wire \uut_sdramtop|module_001|Selector19~0_combout ;
wire \uut_sdramtop|module_001|Selector19~1_combout ;
wire \uut_sdramtop|module_001|cnt_clk_r[5]~19_combout ;
wire \uut_sdramtop|module_001|LessThan0~0_combout ;
wire \uut_sdramtop|module_001|LessThan0~1_combout ;
wire \uut_sdramtop|module_001|cnt_200us[2]~17_combout ;
wire \uut_sdramtop|module_001|cnt_200us[5]~23_combout ;
wire \uut_sdramtop|module_001|cnt_200us[9]~31_combout ;
wire \uut_sdramtop|module_001|Equal1~1_combout ;
wire \uut_sdramtop|module_001|Equal1~2_combout ;
wire \uut_datagene|Equal3~2_combout ;
wire \uut_datagene|Equal3~3_combout ;
wire \uut_datagene|Equal2~1_combout ;
wire \uut_datagene|cntwr[4]~16_combout ;
wire \uut_datagene|cntwr[6]~20_combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ;
wire \uut_sdffifoctrl|uut_rdfifo|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ;
wire \uut_uartctrl|uut_ss|cnt[2]~17_combout ;
wire \uut_sdramtop|module_001|cnt_15us[2]~15_combout ;
wire \uut_sdramtop|module_001|cnt_15us[4]~19_combout ;
wire \uut_sdramtop|module_001|cnt_15us[8]~27_combout ;
wire \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ;
wire \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ;
wire \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ;
wire \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ;
wire \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ;
wire \uut_sdffifoctrl|uut_wrfifo|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ;
wire \uut_datagene|delay[7]~25_combout ;
wire \uut_datagene|delay[11]~33_combout ;