sdr_test_v.sdo

sdram读写

// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP2C5Q208C8 Package PQFP208
// 

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "sdr_test")
  (DATE "11/13/2010 16:15:15")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 9.1 Build 222 10/21/2009 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_sdramtop\|module_001\|work_state_r\.0100)
    (DELAY
      (ABSOLUTE
        (PORT clk (1512:1512:1512) (1512:1512:1512))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1523:1523:1523) (1523:1523:1523))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_sdramtop\|module_001\|work_state_r\.0011)
    (DELAY
      (ABSOLUTE
        (PORT clk (1512:1512:1512) (1512:1512:1512))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1523:1523:1523) (1523:1523:1523))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE uut_sdramtop\|module_002\|WideOr0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1136:1136:1136) (1136:1136:1136))
        (PORT datab (1124:1124:1124) (1124:1124:1124))
        (PORT datac (1145:1145:1145) (1145:1145:1145))
        (PORT datad (1113:1113:1113) (1113:1113:1113))
        (IOPATH dataa combout (651:651:651) (651:651:651))
        (IOPATH datab combout (623:623:623) (623:623:623))
        (IOPATH datac combout (366:366:366) (366:366:366))
        (IOPATH datad combout (206:206:206) (206:206:206))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE uut_sdramtop\|module_002\|Selector15\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (422:422:422) (422:422:422))
        (PORT datab (611:611:611) (611:611:611))
        (PORT datac (1091:1091:1091) (1091:1091:1091))
        (PORT datad (1059:1059:1059) (1059:1059:1059))
        (IOPATH dataa combout (651:651:651) (651:651:651))
        (IOPATH datab combout (624:624:624) (624:624:624))
        (IOPATH datac combout (366:366:366) (366:366:366))
        (IOPATH datad combout (206:206:206) (206:206:206))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE uut_sdramtop\|module_002\|Selector22\~0)
    (DELAY
      (ABSOLUTE
        (PORT datab (1064:1064:1064) (1064:1064:1064))
        (PORT datac (1158:1158:1158) (1158:1158:1158))
        (PORT datad (1908:1908:1908) (1908:1908:1908))
        (IOPATH datab combout (624:624:624) (624:624:624))
        (IOPATH datac combout (366:366:366) (366:366:366))
        (IOPATH datad combout (206:206:206) (206:206:206))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_datagene\|wr_addr\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1519:1519:1519) (1519:1519:1519))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1530:1530:1530) (1530:1530:1530))
        (PORT ena (1468:1468:1468) (1468:1468:1468))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
      (HOLD ena (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE uut_sdramtop\|module_002\|Selector20\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1667:1667:1667) (1667:1667:1667))
        (PORT datac (1201:1201:1201) (1201:1201:1201))
        (PORT datad (769:769:769) (769:769:769))
        (IOPATH dataa combout (615:615:615) (615:615:615))
        (IOPATH datac combout (366:366:366) (366:366:366))
        (IOPATH datad combout (206:206:206) (206:206:206))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_datagene\|rd_addr\[8\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1509:1509:1509) (1509:1509:1509))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1520:1520:1520) (1520:1520:1520))
        (PORT ena (1887:1887:1887) (1887:1887:1887))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
      (HOLD ena (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE uut_sdramtop\|module_002\|Selector19\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1666:1666:1666) (1666:1666:1666))
        (PORT datac (1192:1192:1192) (1192:1192:1192))
        (PORT datad (766:766:766) (766:766:766))
        (IOPATH dataa combout (615:615:615) (615:615:615))
        (IOPATH datac combout (366:366:366) (366:366:366))
        (IOPATH datad combout (206:206:206) (206:206:206))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_datagene\|wr_addr\[9\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1519:1519:1519) (1519:1519:1519))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1530:1530:1530) (1530:1530:1530))
        (PORT ena (1468:1468:1468) (1468:1468:1468))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
      (HOLD ena (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE uut_uartctrl\|uut_tx\|Mux0\~0)
    (DELAY
      (ABSOLUTE
        (PORT dataa (536:536:536) (536:536:536))
        (PORT datab (521:521:521) (521:521:521))
        (PORT datac (1412:1412:1412) (1412:1412:1412))
        (PORT datad (1031:1031:1031) (1031:1031:1031))
        (IOPATH dataa combout (650:650:650) (650:650:650))
        (IOPATH datab combout (624:624:624) (624:624:624))
        (IOPATH datac combout (370:370:370) (370:370:370))
        (IOPATH datad combout (206:206:206) (206:206:206))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE uut_uartctrl\|uut_tx\|Mux0\~1)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1431:1431:1431) (1431:1431:1431))
        (PORT datab (528:528:528) (528:528:528))
        (PORT datac (389:389:389) (389:389:389))
        (PORT datad (1042:1042:1042) (1042:1042:1042))
        (IOPATH dataa combout (651:651:651) (651:651:651))
        (IOPATH datab combout (623:623:623) (623:623:623))
        (IOPATH datac combout (366:366:366) (366:366:366))
        (IOPATH datad combout (206:206:206) (206:206:206))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_led_test\|cnt\[3\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1496:1496:1496) (1496:1496:1496))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1507:1507:1507) (1507:1507:1507))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_led_test\|cnt\[5\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1496:1496:1496) (1496:1496:1496))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1507:1507:1507) (1507:1507:1507))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE uut_led_test\|Equal0\~3)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1154:1154:1154) (1154:1154:1154))
        (PORT datab (464:464:464) (464:464:464))
        (PORT datac (466:466:466) (466:466:466))
        (PORT datad (436:436:436) (436:436:436))
        (IOPATH dataa combout (604:604:604) (604:604:604))
        (IOPATH datab combout (577:577:577) (577:577:577))
        (IOPATH datac combout (370:370:370) (370:370:370))
        (IOPATH datad combout (206:206:206) (206:206:206))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_led_test\|cnt\[16\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1499:1499:1499) (1499:1499:1499))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1510:1510:1510) (1510:1510:1510))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_led_test\|cnt\[18\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1499:1499:1499) (1499:1499:1499))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1510:1510:1510) (1510:1510:1510))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_led_test\|cnt\[19\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1499:1499:1499) (1499:1499:1499))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1510:1510:1510) (1510:1510:1510))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE uut_led_test\|Equal0\~5)
    (DELAY
      (ABSOLUTE
        (PORT dataa (480:480:480) (480:480:480))
        (PORT datab (738:738:738) (738:738:738))
        (PORT datac (464:464:464) (464:464:464))
        (PORT datad (448:448:448) (448:448:448))
        (IOPATH dataa combout (604:604:604) (604:604:604))
        (IOPATH datab combout (577:577:577) (577:577:577))
        (IOPATH datac combout (370:370:370) (370:370:370))
        (IOPATH datad combout (206:206:206) (206:206:206))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_led_test\|cnt\[21\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1499:1499:1499) (1499:1499:1499))
        (PORT datain (108:108:108) (108:108:108))
        (PORT aclr (1510:1510:1510) (1510:1510:1510))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
        (IOPATH (posedge aclr) regout (267:267:267) (267:267:267))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_sdffifoctrl\|uut_rdfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe17\|dffe18a\[0\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1503:1503:1503) (1503:1503:1503))
        (PORT datain (108:108:108) (108:108:108))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (306:306:306))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE uut_sdffifoctrl\|uut_rdfifo\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe17\|dffe18a\[1\])
    (DELAY
      (ABSOLUTE
        (PORT clk (1503:1503:1503) (1503:1503:1503))
        (PORT sdata (903:903:903) (903:903:903))
        (IOPATH (posedge clk) regout (304:304:304) (304:304:304))
      )