sdr_test.fit.summary

来自「sdram读写」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Sat Nov 13 16:14:58 2010
Quartus II Version : 9.1 Build 222 10/21/2009 SJ Full Version
Revision Name : sdr_test
Top-level Entity Name : sdr_test
Family : Cyclone II
Device : EP2C5Q208C8
Timing Models : Final
Total logic elements : 628 / 4,608 ( 14 % )
    Total combinational functions : 534 / 4,608 ( 12 % )
    Dedicated logic registers : 429 / 4,608 ( 9 % )
Total registers : 429
Total pins : 61 / 142 ( 43 % )
Total virtual pins : 0
Total memory bits : 16,384 / 119,808 ( 14 % )
Embedded Multiplier 9-bit elements : 0 / 26 ( 0 % )
Total PLLs : 1 / 2 ( 50 % )