sdr_test.fit.rpt

sdram读写

; Use TimeQuest Timing Analyzer                                              ; On                             ; Off                            ;
; Minimum Core Junction Temperature                                          ; 0                              ;                                ;
; Maximum Core Junction Temperature                                          ; 85                             ;                                ;
; Fit Attempts to Skip                                                       ; 0                              ; 0.0                            ;
; Device I/O Standard                                                        ; 3.3-V LVTTL                    ;                                ;
; Use smart compilation                                                      ; Off                            ; Off                            ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                             ; On                             ;
; Enable compact report table                                                ; Off                            ; Off                            ;
; Router Timing Optimization Level                                           ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                                ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                                   ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                                ; Off                            ; Off                            ;
; Optimize Hold Timing                                                       ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Multi-Corner Timing                                               ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                               ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                            ; Normal compilation             ; Normal compilation             ;
; Optimize Timing for ECOs                                                   ; Off                            ; Off                            ;
; Regenerate full fit report during ECO compiles                             ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                                 ; On                             ; On                             ;
; Limit to One Fitting Attempt                                               ; Off                            ; Off                            ;
; Final Placement Optimizations                                              ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                                ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                              ; 1                              ; 1                              ;
; PCI I/O                                                                    ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                      ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                                  ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                         ; Off                            ; Off                            ;
; Auto Packed Registers                                                      ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                          ; On                             ; On                             ;
; Auto Merge PLLs                                                            ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                          ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting             ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance         ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                               ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                                ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                                  ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                     ; Off                            ; Off                            ;
; Fitter Effort                                                              ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                            ; Normal                         ; Normal                         ;
; Auto Global Clock                                                          ; On                             ; On                             ;
; Auto Global Register Control Signals                                       ; On                             ; On                             ;
; Stop After Congestion Map Generation                                       ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                          ; Off                            ; Off                            ;
; Force Fitter to Avoid Periphery Placement Warnings                         ; Off                            ; Off                            ;
; Use Best Effort Settings for Compilation                                   ; Off                            ; Off                            ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.18        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     1 processor            ; 100.0%      ;
;     2 processors           ;  10.0%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------+
; Ignored Assignments                                                                        ;
+----------+----------------+--------------+----------------+---------------+----------------+
; Name     ; Ignored Entity ; Ignored From ; Ignored To     ; Ignored Value ; Ignored Source ;
+----------+----------------+--------------+----------------+---------------+----------------+
; Location ;                ;              ; clk1           ; PIN_129       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[0]  ; PIN_8         ; QSF Assignment ;
; Location ;                ;              ; flash_addr[10] ; PIN_165       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[11] ; PIN_164       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[12] ; PIN_163       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[13] ; PIN_162       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[14] ; PIN_161       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[15] ; PIN_160       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[16] ; PIN_189       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[17] ; PIN_176       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[18] ; PIN_175       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[19] ; PIN_170       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[1]  ; PIN_188       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[2]  ; PIN_187       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[3]  ; PIN_185       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[4]  ; PIN_182       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[5]  ; PIN_181       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[6]  ; PIN_180       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[7]  ; PIN_179       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[8]  ; PIN_169       ; QSF Assignment ;
; Location ;                ;              ; flash_addr[9]  ; PIN_168       ; QSF Assignment ;