pbch.vht

VHDL实例,适合大家学习使用

-- VHDL test bench created from symbol pbch.sym -- Feb 27 12:00:59 2002

LIBRARY vanmacro;
USE vanmacro.components.ALL;
LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;

entity testbench is
end testbench;

Architecture behavior of testbench is

   signal      CLK : std_logic;
   signal      CLR : std_logic;
   signal      KYF : std_logic;
   signal        a : std_logic;
   signal        b : std_logic;
   signal        c : std_logic;
   signal        d : std_logic;
   signal       dt : std_logic;
   signal        e : std_logic;
   signal        f : std_logic;
   signal        g : std_logic;
   signal     SEG1 : std_logic;
   signal     SEG2 : std_logic;
   signal     SEG3 : std_logic;
   signal     SEG4 : std_logic;
   signal     SEG5 : std_logic;
   signal     SEG6 : std_logic;
   signal     SEG7 : std_logic;
   signal     SEG8 : std_logic;

   component PBCH
      Port (     CLK : In    std_logic;
                 CLR : In    std_logic;
                 KYF : In    std_logic;
                   a : Out   std_logic;
                   b : Out   std_logic;
                   c : Out   std_logic;
                   d : Out   std_logic;
                  dt : Out   std_logic;
                   e : Out   std_logic;
                   f : Out   std_logic;
                   g : Out   std_logic;
                SEG1 : Out   std_logic;
                SEG2 : Out   std_logic;
                SEG3 : Out   std_logic;
                SEG4 : Out   std_logic;
                SEG5 : Out   std_logic;
                SEG6 : Out   std_logic;
                SEG7 : Out   std_logic;
                SEG8 : Out   std_logic );
   end component;

begin
   UUT : PBCH
      Port Map ( a=>a, b=>b, c=>c, CLK=>CLK, CLR=>CLR, d=>d, dt=>dt,
                 e=>e, f=>f, g=>g, KYF=>KYF, SEG1=>SEG1, SEG2=>SEG2,
                 SEG3=>SEG3, SEG4=>SEG4, SEG5=>SEG5, SEG6=>SEG6,
                 SEG7=>SEG7, SEG8=>SEG8 );

-- *** Test Bench - User Defined Section ***
   TB : process
   begin
      wait; -- will wait forever
   end process;
-- *** End Test Bench - User Defined Section ***

end behavior;