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Frequency Analysis Report:
-------------------------
Design Name: PB
Part Name: ispLSI1032E-70LJ84
This report contains the maximum frequency at which the design
can be operated. It also lists the path that determines the
maximum frequency and the number of GLB levels.
The remaining internal register paths and their frequencies
are also listed, if the source and the registers are driven
by the same reference clock.
Maximum Operating Frequency: 65 MHz
The clock period is 15.50.
Clock period = path delay + clock-to-output delay + setup time
path delay: 12.10
clock-to-output delay: 2.40
setup time: 1.00
The following path determines the frequency:
Startpoint: GLB_I22_Q0_Q_BLIF/Q0
(edge-triggered flip-flop)
Endpoint: GLB_I22_Q2_Q_BLIF/D0
(edge-triggered flip-flop)
No. of GLB Levels: 1
Internal Register Paths and Frequencies:
Source Source Destination Destination Clock Frequency # of GLB
Reference Register Reference Register Period [MHz] Levels
Clock Name Clock Name [ns]
==----------------------------------------------------------------------------------------------------------------
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *2/D0 15.40 ---- 1
CLR GLB_...BLIF *2/Q0 CLR GLB_...BLIF *2/D0 14.40 69 1
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *3/D0 15.40 ---- 1
CLR GLB_...BLIF *4/Q0 CLR GLB_...BLIF *3/D0 15.10 66 1
CLR GLB_...BLIF *5/Q0 CLR GLB_...BLIF *3/D0 15.10 66 1
CLR GLB_...BLIF *6/Q0 CLR GLB_...BLIF *3/D0 14.90 67 1
CLR GLB_...BLIF *3/Q0 CLR GLB_...BLIF *3/D0 13.70 73 1
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *7/D0 15.40 ---- 1
CLR GLB_...BLIF *8/Q0 CLR GLB_...BLIF *7/D0 15.10 66 1
CLR GLB_...BLIF *9/Q0 CLR GLB_...BLIF *7/D0 15.00 67 1
CLR GLB_...BLIF *7/Q0 CLR GLB_...BLIF *7/D0 13.70 73 1
CLR GLB_...BLIF *10/Q0 CLR GLB_...BLIF *7/D0 13.70 73 1
CLK GLB_...BLIF *11/Q0 CLK GLB_...BLIF *12/D0 15.50 65 1
CLK GLB_...BLIF *12/Q0 CLK GLB_...BLIF *12/D0 13.70 73 1
CLK GLB_...BLIF *13/Q0 CLK GLB_...BLIF *12/D0 13.70 73 1
CLK GLB_...BLIF *1/Q0 GLB_...BLIF *14 GLB_...BLIF *15/CLK 5.70 ---- 1
CLK GLB_...BLIF *1/Q0 GLB_...BLIF *14 GLB_...BLIF *15/D0 15.40 ---- 1
CLR GLB_...BLIF *16/Q0 GLB_...BLIF *14 GLB_...BLIF *15/D0 15.30 ---- 1
CLR GLB_...BLIF *17/Q0 GLB_...BLIF *14 GLB_...BLIF *15/D0 15.30 ---- 1
CLR GLB_...BLIF *18/Q0 GLB_...BLIF *14 GLB_...BLIF *15/D0 15.20 ---- 1
CLR GLB_...BLIF *19/Q0 GLB_...BLIF *14 GLB_...BLIF *15/D0 15.10 ---- 1
GLB_...BLIF *20 GLB_...BLIF *21/Q0 GLB_...BLIF *14 GLB_...BLIF *15/D0 15.00 67 1
GLB_...BLIF *14 GLB_...BLIF *15/Q0 GLB_...BLIF *14 GLB_...BLIF *15/D0 13.70 73 1
GLB_...BLIF *22 GLB_...BLIF *23/Q0 GLB_...BLIF *14 GLB_...BLIF *15/D0 13.70 73 1
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *18/D0 13.90 ---- 1
CLR GLB_...BLIF *17/Q0 CLR GLB_...BLIF *18/D0 13.80 72 1
CLR GLB_...BLIF *18/Q0 CLR GLB_...BLIF *18/D0 13.70 73 1
CLR GLB_...BLIF *19/Q0 CLR GLB_...BLIF *18/D0 12.20 82 1
CLK GLB_...BLIF *1/Q0 GLB_...BLIF *24 GLB_...BLIF *25/CLK 5.70 ---- 1
CLK GLB_...BLIF *1/Q0 GLB_...BLIF *24 GLB_...BLIF *25/D0 15.40 ---- 1
CLR GLB_...BLIF *9/Q0 GLB_...BLIF *24 GLB_...BLIF *25/D0 15.30 ---- 1
CLR GLB_...BLIF *7/Q0 GLB_...BLIF *24 GLB_...BLIF *25/D0 15.20 ---- 1
CLR GLB_...BLIF *8/Q0 GLB_...BLIF *24 GLB_...BLIF *25/D0 15.10 ---- 1
GLB_...BLIF *24 GLB_...BLIF *25/Q0 GLB_...BLIF *24 GLB_...BLIF *25/D0 15.00 67 1
CLR GLB_...BLIF *10/Q0 GLB_...BLIF *24 GLB_...BLIF *25/D0 15.00 ---- 1
GLB_...BLIF *26 GLB_...BLIF *27/Q0 GLB_...BLIF *24 GLB_...BLIF *25/D0 13.70 73 1
GLB_...BLIF *28 GLB_...BLIF *29/Q0 GLB_...BLIF *24 GLB_...BLIF *25/D0 13.70 73 1
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *6/D0 15.40 ---- 1
CLR GLB_...BLIF *6/Q0 CLR GLB_...BLIF *6/D0 15.20 66 1
CLR GLB_...BLIF *4/Q0 CLR GLB_...BLIF *6/D0 15.10 66 1
CLR GLB_...BLIF *5/Q0 CLR GLB_...BLIF *6/D0 15.10 66 1
CLR GLB_...BLIF *3/Q0 CLR GLB_...BLIF *6/D0 13.70 73 1
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *9/D0 15.40 ---- 1
CLR GLB_...BLIF *9/Q0 CLR GLB_...BLIF *9/D0 15.30 65 1
CLR GLB_...BLIF *8/Q0 CLR GLB_...BLIF *9/D0 15.10 66 1
CLR GLB_...BLIF *10/Q0 CLR GLB_...BLIF *9/D0 13.70 73 1
CLR GLB_...BLIF *7/Q0 CLR GLB_...BLIF *9/D0 13.70 73 1
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *19/D0 15.40 ---- 1
CLR GLB_...BLIF *19/Q0 CLR GLB_...BLIF *19/D0 13.00 77 1
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *8/D0 15.40 ---- 1
CLR GLB_...BLIF *8/Q0 CLR GLB_...BLIF *8/D0 14.40 69 1
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *30/D0 15.40 ---- 1
CLR GLB_...BLIF *30/Q0 CLR GLB_...BLIF *30/D0 15.30 65 1
CLR GLB_...BLIF *31/Q0 CLR GLB_...BLIF *30/D0 15.30 65 1
CLR GLB_...BLIF *2/Q0 CLR GLB_...BLIF *30/D0 15.10 66 1
CLR GLB_...BLIF *32/Q0 CLR GLB_...BLIF *30/D0 13.70 73 1
CLK GLB_...BLIF *11/Q0 CLK GLB_...BLIF *11/D0 14.80 68 1
CLK GLB_...BLIF *1/Q0 CLR GLB_...BLIF *5/D0 15.40 ---- 1
CLR GLB_...BLIF *5/Q0 CLR GLB_...BLIF *5/D0 13.00 77 1
CLK GLB_...BLIF *1/Q0 GLB_...BLIF *20 GLB_...BLIF *21/CLK 5.70 ---- 1
GLB_...BLIF *20 GLB_...BLIF *21/Q0 GLB_...BLIF *20 GLB_...BLIF *21/D0 15.00 67 1
CLK GLB_...BLIF *1/Q0 GLB_...BLIF *20 GLB_...BLIF *21/D0 14.70 ---- 1
CLR GLB_...BLIF *16/Q0 GLB_...BLIF *20 GLB_...BLIF *21/D0 14.60 ---- 1
CLR GLB_...BLIF *17/Q0 GLB_...BLIF *20 GLB_...BLIF *21/D0 14.60 ---- 1
CLR GLB_...BLIF *18/Q0 GLB_...BLIF *20 GLB_...BLIF *21/D0 14.50 ---- 1
CLR GLB_...BLIF *19/Q0 GLB_...BLIF *20 GLB_...BLIF *21/D0 14.40 ---- 1
CLK GLB_...BLIF *1/Q0 GLB_...BLIF *28 GLB_...BLIF *29/CLK 5.70 ---- 1
CLK GLB_...BLIF *1/Q0 GLB_...BLIF *28 GLB_...BLIF *29/D0 14.70 ---- 1
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