key.lst

VHDL实例,适合大家学习使用

0002 |CLK,K   PIN;
0003 |EN      PIN;
0004 |SS1,SS0 PIN ISTYPE 'REG';
0005 |SS = [SS1,SS0];
0006 |S0 = ^B00;S1 = ^B01;S2 = ^B10;S3 = ^B11;
0007 |EQUATIONS
0008 |SS.CLK = CLK;
0009 |
0010 |STATE_DIAGRAM SS
0011 |  STATE S0:EN = 0;
0012 |        CASE K==1:S0;
0013 |             K==0:S1;
0014 |        ENDCASE
0015 |
0016 |  STATE S1:EN = 1;
0017 |        CASE K==0:S1;
0018 |             K==1:S2;
0019 |        ENDCASE
0020 |
0021 |  STATE S2:EN = 1;
0022 |        CASE K==0:S2;
0023 |             K==1:S3;
0024 |        ENDCASE
0025 |
0026 |  STATE S3:EN = 0;
0027 |        CASE K==0:S3;
0028 |             K==1:S0;
0029 |        ENDCASE
0030 |END 
0031 |