key.abt

VHDL实例,适合大家学习使用

MODULE key

" TOOL:     ispDesignEXPERT
" DATE:     Wed Feb 27 10:40:07 2002 
" TITLE:    
" MODULE:   key
" DESIGN:   key
" FILENAME: KEY.abt
" PROJECT:  pb
" VERSION:  8.4

" NOTE: DO NOT EDIT THIS FILE DIRECTLY.
" This file is auto generated by ispDesignEXPERT System.
" It can be removed or overwritten automatically.
" If you want to edit this file, copy it to another file or 
" rename it with different file extension first. 


" Inputs
    K pin;
    CLK pin;


" Outputs
    SS1 pin;
    SS0 pin;
    EN pin;


" Bidirs



Test_vectors
([K,CLK] -> [SS1,SS0,EN])


END