pb.rp-

VHDL实例,适合大家学习使用

ispEXPERT Compiler Release 8.4.06.39, Nov  9 2000 13:09:01


Design Parameters
-----------------

EFFORT:                         MEDIUM (2)
IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16
MAX_GLB_OUT:                    4
OS_VERSION:                     Windows 98
PARAM_FILE:                     '_pb'
PIN_FILE:                       'pb.xpn'
STRATEGY:                       DELAY
TIMING_ANALYZER:                FREQUENCY SETUP_HOLD CLOCK_TO_OUTPUT PRIMARY_IN_TO_OUT 
USE_GLOBAL_RESET:               ON
XOR:                            OFF


Design Specification
--------------------

Design:                         pb
Part:                           ispLSI1032E-70LJ84


ISP:                            ON
PULL:                           UP
SECURITY:                       OFF
SLOWSLEW:                       OFF


Number of Critical Pins:        0
Number of Free Pins:            19
Number of Locked Pins:          0
Number of Reserved Pins:        0


Input Pins

    Pin Name                Pin Attribute

        CLK                     PULLUP
        CLR                     PULLUP
        KEY                     PULLUP


Output Pins

    Pin Name                Pin Attribute

        A                       PULLUP
        B                       PULLUP
        C                       PULLUP
        D                       PULLUP
        DT                      PULLUP
        E                       PULLUP
        F                       PULLUP
        G                       PULLUP
        SEG1                    PULLUP
        SEG2                    PULLUP
        SEG3                    PULLUP
        SEG4                    PULLUP
        SEG5                    PULLUP
        SEG6                    PULLUP
        SEG7                    PULLUP
        SEG8                    PULLUP


Pre-Route Design Statistics
---------------------------

Number of Macrocells:           41
Number of GLBs:                 12
Number of I/Os:                 18
Number of Nets:                 41

Number of Free Inputs:          2
Number of Free Outputs:         16
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    0
Number of Locked DIs:           0
Number of Locked Outputs:       0
Number of Locked Three-States:  0
Number of Locked Bidi's:        0

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      0


GLB Utilization (Out of 32):	37%
I/O Utilization (Out of 68):	26%
Net Utilization (Out of 196):	20%


Nets with Fanout of  1:         9
Nets with Fanout of  2:         5
Nets with Fanout of  3:         6
Nets with Fanout of  4:         7
Nets with Fanout of  5:         9
Nets with Fanout of  6:         2
Nets with Fanout of  7:         3

Average Fanout per Net:         3.49


GLBs with  7 Input(s):          2
GLBs with  8 Input(s):          1
GLBs with  9 Input(s):          1
GLBs with 10 Input(s):          2
GLBs with 12 Input(s):          1
GLBs with 13 Input(s):          2
GLBs with 14 Input(s):          1
GLBs with 15 Input(s):          1
GLBs with 16 Input(s):          1

Average Inputs per GLB:         11.17


GLBs with  2 Output(s):         1
GLBs with  3 Output(s):         5
GLBs with  4 Output(s):         6

Average Outputs per GLB:        3.42


Number of GLB Registers:        26
Number of IOC Registers:        0


Post-Route Design Implementation
--------------------------------

Number of Macrocells:		41
Number of GLBs:			12
Number of IOCs:			18
Number of DIs:			0
Number of GLB Levels:		2


Clock GLB glb00, C0

    12 Input(s)
        (CLK.O, CLKX, I7), (CLR.O, CLRX, I6), (glb09.O2, 
        I22_Q0_Q_BLIF, I9), (glb09.O1, I22_Q1_Q_BLIF, I10), (glb09.O0, 
        I22_Q2_Q_BLIF, I11), (glb05.O2, N_14_Q_BLIF, I2), (glb10.O3, 
        N_18_Q_BLIF, I15), (glb08.O2, N_21_Q_BLIF, I5), (glb06.O2, 
        N_25_Q_BLIF, I14), (glb07.O3, N_28_Q_BLIF, I4), (glb10.O1, 
        N_32_Q_BLIF, I13), (glb00.O0, N_36_Q_BLIF, I16)
    3 Output(s)
        (N_36_Q_BLIF, O0), (N_11, O2), (BUF_1228, O1)
    10 Product Term(s)

    Output N_36_Q_BLIF

        2 Input(s)
            CLKX, N_36_Q_BLIF
        9 Fanout(s)
            glb06.I0, glb08.I4, glb08.CLK1, glb11.I4, glb00.I16,
            glb07.I15, glb07.CLK1, glb05.I15, glb10.I11
        2 Product Term(s)
        1 GLB Level(s)

        N_36_Q_BLIF.D = (N_36_Q_BLIF)
            $ VCC
        N_36_Q_BLIF.C = CLKX
        N_36_Q_BLIF.R = CLKX

    Output N_11

        9 Input(s)
            N_25_Q_BLIF, N_18_Q_BLIF, N_32_Q_BLIF, I22_Q1_Q_BLIF,
            I22_Q0_Q_BLIF, I22_Q2_Q_BLIF, N_21_Q_BLIF, N_28_Q_BLIF,
            N_14_Q_BLIF
        5 Fanout(s)
            glb09.I2, glb04.I2, glb03.I13, glb01.I13, glb02.I13
        6 Product Term(s)
        1 GLB Level(s)

        N_11 = (N_14_Q_BLIF & !I22_Q0_Q_BLIF & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & N_18_Q_BLIF & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & I22_Q1_Q_BLIF & N_21_Q_BLIF
            & !I22_Q2_Q_BLIF
            # I22_Q1_Q_BLIF & N_25_Q_BLIF & !I22_Q0_Q_BLIF
            & !I22_Q2_Q_BLIF
            # I22_Q0_Q_BLIF & I22_Q2_Q_BLIF & N_28_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q2_Q_BLIF & N_32_Q_BLIF & !I22_Q0_Q_BLIF
            & !I22_Q1_Q_BLIF)

    Output BUF_1228

        1 Input(s)
            CLRX
        4 Fanout(s)
            glb06.CLK2, glb11.CLK2, glb05.CLK2, glb10.CLK2
        1 Product Term(s)
        1 GLB Level(s)

        BUF_1228 = CLRX


GLB glb01, D4

    10 Input(s)
        (glb09.O2, I22_Q0_Q_BLIF, I9), (glb09.O1, I22_Q1_Q_BLIF, I10), 
        (glb09.O0, I22_Q2_Q_BLIF, I11), (glb05.O3, N_13_Q_BLIF, I8), 
        (glb11.O2, N_17_Q_BLIF, I2), (glb06.O3, N_24_Q_BLIF, I15), 
        (glb10.O2, N_31_Q_BLIF, I14), (glb02.O0, N_10, I7), (glb00.O2, 
        N_11, I13), (glb07.O0, N_9, I3)
    3 Output(s)
        (VCC_1398, O0), (DEF_1119, O2), (B_COM_BLIF, O1)
    19 Product Term(s)

    Output VCC_1398

        0 Input(s)
        1 Fanout(s)
            DT.IR
        0 Product Term(s)
        0 GLB Level(s)

        VCC_1398 = VCC

    Output DEF_1119

        10 Input(s)
            N_9, N_24_Q_BLIF, N_17_Q_BLIF, N_10, N_11, N_13_Q_BLIF,
            I22_Q1_Q_BLIF, I22_Q0_Q_BLIF, N_31_Q_BLIF, I22_Q2_Q_BLIF
        1 Fanout(s)
            G.IR
        10 Product Term(s)
        2 GLB Level(s)

        DEF_1119 = (N_10 & !N_11
            # N_13_Q_BLIF & !I22_Q0_Q_BLIF & !I22_Q2_Q_BLIF & !N_10
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & N_17_Q_BLIF & !I22_Q2_Q_BLIF & !N_10
            & !I22_Q1_Q_BLIF
            # I22_Q1_Q_BLIF & N_24_Q_BLIF & !I22_Q0_Q_BLIF
            & !I22_Q2_Q_BLIF & !N_10
            # I22_Q2_Q_BLIF & N_31_Q_BLIF & !I22_Q0_Q_BLIF & !N_10
            & !I22_Q1_Q_BLIF
            # N_13_Q_BLIF & !I22_Q0_Q_BLIF & N_9 & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & N_17_Q_BLIF & N_9 & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q1_Q_BLIF & N_24_Q_BLIF & !I22_Q0_Q_BLIF & N_9
            & !I22_Q2_Q_BLIF
            # I22_Q2_Q_BLIF & N_31_Q_BLIF & !I22_Q0_Q_BLIF & N_9
            & !I22_Q1_Q_BLIF)
            $ N_11 & !N_9

    Output B_COM_BLIF

        10 Input(s)
            N_9, N_24_Q_BLIF, N_17_Q_BLIF, N_10, N_11, N_13_Q_BLIF,
            I22_Q1_Q_BLIF, I22_Q0_Q_BLIF, N_31_Q_BLIF, I22_Q2_Q_BLIF
        1 Fanout(s)
            B.IR
        9 Product Term(s)
        2 GLB Level(s)

        B_COM_BLIF = (N_10 & N_11 & !N_9
            # N_13_Q_BLIF & !I22_Q0_Q_BLIF & N_10 & N_9 & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & N_17_Q_BLIF & N_10 & N_9 & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q1_Q_BLIF & N_24_Q_BLIF & !I22_Q0_Q_BLIF & N_10 & N_9
            & !I22_Q2_Q_BLIF
            # I22_Q2_Q_BLIF & N_31_Q_BLIF & !I22_Q0_Q_BLIF & N_10 & N_9
            & !I22_Q1_Q_BLIF
            # N_13_Q_BLIF & !I22_Q0_Q_BLIF & N_11 & !I22_Q2_Q_BLIF & !N_9
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & N_17_Q_BLIF & N_11 & !I22_Q2_Q_BLIF & !N_9
            & !I22_Q1_Q_BLIF
            # I22_Q1_Q_BLIF & N_24_Q_BLIF & !I22_Q0_Q_BLIF & N_11
            & !I22_Q2_Q_BLIF & !N_9
            # I22_Q2_Q_BLIF & N_31_Q_BLIF & !I22_Q0_Q_BLIF & N_11 & !N_9
            & !I22_Q1_Q_BLIF)


GLB glb02, D7

    16 Input(s)
        (glb09.O2, I22_Q0_Q_BLIF, I9), (glb09.O1, I22_Q1_Q_BLIF, I10), 
        (glb09.O0, I22_Q2_Q_BLIF, I11), (glb05.O3, N_13_Q_BLIF, I8), 
        (glb11.O3, N_15_Q_BLIF, I3), (glb11.O2, N_17_Q_BLIF, I2), 
        (glb11.O1, N_19_Q_BLIF, I1), (glb08.O1, N_22_Q_BLIF, I6), 
        (glb06.O3, N_24_Q_BLIF, I15), (glb11.O0, N_26_Q_BLIF, I0), 
        (glb07.O2, N_29_Q_BLIF, I5), (glb10.O2, N_31_Q_BLIF, I14), 
        (glb10.O0, N_33_Q_BLIF, I12), (glb02.O0, N_10, I16), (glb00.O2, 
        N_11, I13), (glb07.O0, N_9, I7)
    2 Output(s)
        (N_10, O0), (D_COM_BLIF, O1)
    19 Product Term(s)

    Output N_10

        9 Input(s)
            N_26_Q_BLIF, N_33_Q_BLIF, N_29_Q_BLIF, I22_Q1_Q_BLIF,
            I22_Q0_Q_BLIF, I22_Q2_Q_BLIF, N_22_Q_BLIF, N_19_Q_BLIF,
            N_15_Q_BLIF
        4 Fanout(s)
            glb04.I8, glb03.I7, glb01.I7, glb02.I16
        6 Product Term(s)
        1 GLB Level(s)

        N_10 = (N_15_Q_BLIF & !I22_Q0_Q_BLIF & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & N_19_Q_BLIF & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & I22_Q1_Q_BLIF & N_22_Q_BLIF
            & !I22_Q2_Q_BLIF
            # I22_Q1_Q_BLIF & N_26_Q_BLIF & !I22_Q0_Q_BLIF
            & !I22_Q2_Q_BLIF
            # I22_Q0_Q_BLIF & I22_Q2_Q_BLIF & N_29_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q2_Q_BLIF & N_33_Q_BLIF & !I22_Q0_Q_BLIF
            & !I22_Q1_Q_BLIF)

    Output D_COM_BLIF

        10 Input(s)
            N_9, N_24_Q_BLIF, N_17_Q_BLIF, N_10, N_11, N_13_Q_BLIF,
            I22_Q1_Q_BLIF, I22_Q0_Q_BLIF, N_31_Q_BLIF, I22_Q2_Q_BLIF
        1 Fanout(s)
            D.IR
        13 Product Term(s)
        2 GLB Level(s)

        D_COM_BLIF = (N_10 & N_11 & N_9
            # N_9 & !N_10 & !N_11
            # I22_Q0_Q_BLIF & I22_Q1_Q_BLIF & N_11 & !N_10
            # I22_Q0_Q_BLIF & I22_Q2_Q_BLIF & N_11 & !N_10
            # I22_Q1_Q_BLIF & I22_Q2_Q_BLIF & N_11 & !N_10
            # I22_Q0_Q_BLIF & N_11 & !N_17_Q_BLIF & !N_10
            # I22_Q1_Q_BLIF & N_11 & !N_24_Q_BLIF & !N_10
            # I22_Q2_Q_BLIF & N_11 & !N_31_Q_BLIF & !N_10
            # !I22_Q0_Q_BLIF & N_11 & !I22_Q2_Q_BLIF & !N_13_Q_BLIF
            & !N_10 & !I22_Q1_Q_BLIF
            # N_13_Q_BLIF & !I22_Q0_Q_BLIF & N_10 & !I22_Q2_Q_BLIF & !N_9
            & !N_11 & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & N_17_Q_BLIF & N_10 & !I22_Q2_Q_BLIF & !N_9
            & !N_11 & !I22_Q1_Q_BLIF
            # I22_Q1_Q_BLIF & N_24_Q_BLIF & !I22_Q0_Q_BLIF & N_10
            & !I22_Q2_Q_BLIF & !N_9 & !N_11
            # I22_Q2_Q_BLIF & N_31_Q_BLIF & !I22_Q0_Q_BLIF & N_10 & !N_9
            & !N_11 & !I22_Q1_Q_BLIF)


GLB glb03, C4

    13 Input(s)
        (glb09.O2, I22_Q0_Q_BLIF, I2), (glb09.O1, I22_Q1_Q_BLIF, I10), 
        (glb09.O0, I22_Q2_Q_BLIF, I11), (glb11.O3, N_15_Q_BLIF, I8), 
        (glb11.O1, N_19_Q_BLIF, I1), (glb08.O1, N_22_Q_BLIF, I6), 
        (glb11.O0, N_26_Q_BLIF, I0), (glb07.O2, N_29_Q_BLIF, I5), 
        (glb10.O0, N_33_Q_BLIF, I12), (glb02.O0, N_10, I7), (glb00.O2, 
        N_11, I13), (glb04.O2, N_12, I9), (glb07.O0, N_9, I3)
    4 Output(s)
        (F_COM_BLIF, O0), (A_COM_BLIF, O2), (AND_1121_part2, O1), 
        (AND_1121_part1, O3)
    20 Product Term(s)

    Output F_COM_BLIF

        12 Input(s)
            N_9, N_26_Q_BLIF, N_11, N_33_Q_BLIF, N_29_Q_BLIF,
            I22_Q1_Q_BLIF, I22_Q0_Q_BLIF, N_12, I22_Q2_Q_BLIF,
            N_22_Q_BLIF, N_19_Q_BLIF, N_15_Q_BLIF
        1 Fanout(s)
            F.IR
        14 Product Term(s)
        2 GLB Level(s)

        F_COM_BLIF = (N_9 & !N_11
            # N_15_Q_BLIF & !I22_Q0_Q_BLIF & N_9 & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & N_19_Q_BLIF & N_9 & !I22_Q2_Q_BLIF
            & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & I22_Q1_Q_BLIF & N_22_Q_BLIF & N_9
            & !I22_Q2_Q_BLIF
            # I22_Q1_Q_BLIF & N_26_Q_BLIF & !I22_Q0_Q_BLIF & N_9
            & !I22_Q2_Q_BLIF
            # I22_Q0_Q_BLIF & I22_Q2_Q_BLIF & N_29_Q_BLIF & N_9
            & !I22_Q1_Q_BLIF
            # I22_Q2_Q_BLIF & N_33_Q_BLIF & !I22_Q0_Q_BLIF & N_9
            & !I22_Q1_Q_BLIF
            # N_15_Q_BLIF & !I22_Q0_Q_BLIF & !I22_Q2_Q_BLIF & !N_12
            & !N_11 & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & N_19_Q_BLIF & !I22_Q2_Q_BLIF & !N_12
            & !N_11 & !I22_Q1_Q_BLIF
            # I22_Q0_Q_BLIF & I22_Q1_Q_BLIF & N_22_Q_BLIF
            & !I22_Q2_Q_BLIF & !N_12 & !N_11
            # I22_Q1_Q_BLIF & N_26_Q_BLIF & !I22_Q0_Q_BLIF
            & !I22_Q2_Q_BLIF & !N_12 & !N_11
            # I22_Q0_Q_BLIF & I22_Q2_Q_BLIF & N_29_Q_BLIF & !N_12 & !N_11
            & !I22_Q1_Q_BLIF
            # I22_Q2_Q_BLIF & N_33_Q_BLIF & !I22_Q0_Q_BLIF & !N_12
            & !N_11 & !I22_Q1_Q_BLIF)
            $ N_12 & N_9

    Output A_COM_BLIF

        4 Input(s)
            N_9, N_10, N_11, N_12
        1 Fanout(s)
            A.IR
        4 Product Term(s)
        2 GLB Level(s)

        A_COM_BLIF = N_11 & N_12 & N_9 & !N_10
            # N_10 & N_12 & N_9 & !N_11
            # N_9 & !N_10 & !N_12 & !N_11
            # N_11 & !N_10 & !N_12 & !N_9

    Output AND_1121_part2

        2 Input(s)
            I22_Q1_Q_BLIF, I22_Q2_Q_BLIF
        2 Fanout(s)
            SEG5.IR, SEG3.IR
        1 Product Term(s)
        1 GLB Level(s)

        AND_1121_part2 = I22_Q1_Q_BLIF & I22_Q2_Q_BLIF

    Output AND_1121_part1

        2 Input(s)
            I22_Q1_Q_BLIF, I22_Q2_Q_BLIF
        3 Fanout(s)
            SEG6.IR, SEG4.IR, SEG1.IR
        1 Product Term(s)
        1 GLB Level(s)

        AND_1121_part1 = I22_Q1_Q_BLIF & I22_Q2_Q_BLIF


GLB glb04, B0

    10 Input(s)
        (glb09.O2, I22_Q0_Q_BLIF, I6), (glb09.O1, I22_Q1_Q_BLIF, I5), 
        (glb09.O0, I22_Q2_Q_BLIF, I4), (glb05.O3, N_13_Q_BLIF, I7), 
        (glb11.O2, N_17_Q_BLIF, I13), (glb06.O3, N_24_Q_BLIF, I0),