pb.laf

VHDL实例,适合大家学习使用

   PIN ZN0 OUT GATE_I26_Q1_D_REG_N_1;
   PIN A0 IN T__57;
 END;
 SYM XNOR2 GATE_I26_Q2_D_REG_U1;
   PIN ZN0 OUT I26_Q2_D_REG;
   PIN A0 IN I26_Q2_Q_BLIF;
   PIN A1 IN T__45;
 END;
 SYM NAND2 GATE_I26_Q3_D_REG_I_3;
   PIN ZN0 OUT I26_Q3_D_REG;
   PIN A0 IN GATE_I26_Q3_D_REG_N_1;
   PIN A1 IN GATE_I26_Q3_D_REG_N_2;
 END;
 SYM INV GATE_I26_Q3_D_REG_I_2;
   PIN ZN0 OUT GATE_I26_Q3_D_REG_N_2;
   PIN A0 IN T__54;
 END;
 SYM INV GATE_I26_Q3_D_REG_I_1;
   PIN ZN0 OUT GATE_I26_Q3_D_REG_N_1;
   PIN A0 IN T__53;
 END;
 SYM XNOR2 GATE_I25_SS1_D_REG_U1;
   PIN ZN0 OUT I25_SS1_D_REG;
   PIN A0 IN I25_SS1_Q_BLIF;
   PIN A1 IN T__47;
 END;
 SYM LXOR2 GATE_I25_SS0_D_REG_U1;
   PIN Z0 OUT I25_SS0_D_REG;
   PIN A0 IN IN_KEY_U1_Z0;
   PIN A1 IN T__48;
 END;
 SYM NAND2 GATE_I22_Q2_D_REG_I_3;
   PIN ZN0 OUT I22_Q2_D_REG;
   PIN A0 IN GATE_I22_Q2_D_REG_N_1;
   PIN A1 IN GATE_I22_Q2_D_REG_N_2;
 END;
 SYM INV GATE_I22_Q2_D_REG_I_2;
   PIN ZN0 OUT GATE_I22_Q2_D_REG_N_2;
   PIN A0 IN T__52;
 END;
 SYM INV GATE_I22_Q2_D_REG_I_1;
   PIN ZN0 OUT GATE_I22_Q2_D_REG_N_1;
   PIN A0 IN T__51;
 END;
 SYM NAND2 GATE_I22_Q1_D_REG_I_3;
   PIN ZN0 OUT I22_Q1_D_REG;
   PIN A0 IN GATE_I22_Q1_D_REG_N_1;
   PIN A1 IN GATE_I22_Q1_D_REG_N_2;
 END;
 SYM INV GATE_I22_Q1_D_REG_I_2;
   PIN ZN0 OUT GATE_I22_Q1_D_REG_N_2;
   PIN A0 IN T__50;
 END;
 SYM INV GATE_I22_Q1_D_REG_I_1;
   PIN ZN0 OUT GATE_I22_Q1_D_REG_N_1;
   PIN A0 IN T__49;
 END;
 SYM INV GATE_I22_Q0_D_REG_I_1;
   PIN ZN0 OUT I22_Q0_D_REG;
   PIN A0 IN I22_Q0_Q_BLIF;
 END;
 SYM NAND2 GATE_T__0_I_3;
   PIN ZN0 OUT T__0;
   PIN A0 IN GATE_T__0_N_1;
   PIN A1 IN GATE_T__0_N_2;
 END;
 SYM INV GATE_T__0_I_2;
   PIN ZN0 OUT GATE_T__0_N_2;
   PIN A0 IN T__111;
 END;
 SYM INV GATE_T__0_I_1;
   PIN ZN0 OUT GATE_T__0_N_1;
   PIN A0 IN T__110;
 END;
 SYM XNOR2 GATE_T__1_U1;
   PIN ZN0 OUT T__1;
   PIN A0 IN N_12;
   PIN A1 IN N_11;
 END;
 SYM NAND2 GATE_T__2_I_3;
   PIN ZN0 OUT T__2;
   PIN A0 IN GATE_T__2_N_1;
   PIN A1 IN GATE_T__2_N_2;
 END;
 SYM INV GATE_T__2_I_2;
   PIN ZN0 OUT GATE_T__2_N_2;
   PIN A0 IN N_12;
 END;
 SYM INV GATE_T__2_I_1;
   PIN ZN0 OUT GATE_T__2_N_1;
   PIN A0 IN N_10;
 END;
 SYM NAND2 GATE_T__3_I_3;
   PIN ZN0 OUT T__3;
   PIN A0 IN GATE_T__3_N_1;
   PIN A1 IN GATE_T__3_N_2;
 END;
 SYM INV GATE_T__3_I_2;
   PIN ZN0 OUT GATE_T__3_N_2;
   PIN A0 IN T__105;
 END;
 SYM INV GATE_T__3_I_1;
   PIN ZN0 OUT GATE_T__3_N_1;
   PIN A0 IN T__104;
 END;
 SYM XNOR2 GATE_T__4_U1;
   PIN ZN0 OUT T__4;
   PIN A0 IN N_11;
   PIN A1 IN N_10;
 END;
 SYM XNOR2 GATE_T__5_U1;
   PIN ZN0 OUT T__5;
   PIN A0 IN N_9;
   PIN A1 IN T__6;
 END;
 SYM NAND2 GATE_T__6_I_3;
   PIN ZN0 OUT T__6;
   PIN A0 IN GATE_T__6_N_1;
   PIN A1 IN N_11;
 END;
 SYM INV GATE_T__6_I_1;
   PIN ZN0 OUT GATE_T__6_N_1;
   PIN A0 IN N_10;
 END;
 SYM NAND2 GATE_T__7_I_3;
   PIN ZN0 OUT T__7;
   PIN A0 IN GATE_T__7_N_1;
   PIN A1 IN GATE_T__7_N_2;
 END;
 SYM INV GATE_T__7_I_2;
   PIN ZN0 OUT GATE_T__7_N_2;
   PIN A0 IN T__98;
 END;
 SYM INV GATE_T__7_I_1;
   PIN ZN0 OUT GATE_T__7_N_1;
   PIN A0 IN T__97;
 END;
 SYM NAND2 GATE_T__8_I_3;
   PIN ZN0 OUT T__8;
   PIN A0 IN GATE_T__8_N_1;
   PIN A1 IN N_11;
 END;
 SYM INV GATE_T__8_I_1;
   PIN ZN0 OUT GATE_T__8_N_1;
   PIN A0 IN N_10;
 END;
 SYM NAND2 GATE_T__9_I_3;
   PIN ZN0 OUT T__9;
   PIN A0 IN GATE_T__9_N_1;
   PIN A1 IN GATE_T__9_N_2;
 END;
 SYM INV GATE_T__9_I_2;
   PIN ZN0 OUT GATE_T__9_N_2;
   PIN A0 IN T__94;
 END;
 SYM INV GATE_T__9_I_1;
   PIN ZN0 OUT GATE_T__9_N_1;
   PIN A0 IN T__93;
 END;
 SYM NAND2 GATE_T__10_I_3;
   PIN ZN0 OUT T__10;
   PIN A0 IN GATE_T__10_N_1;
   PIN A1 IN GATE_T__10_N_2;
 END;
 SYM INV GATE_T__10_I_2;
   PIN ZN0 OUT GATE_T__10_N_2;
   PIN A0 IN T__141;
 END;
 SYM INV GATE_T__10_I_1;
   PIN ZN0 OUT GATE_T__10_N_1;
   PIN A0 IN T__140;
 END;
 SYM NAND2 GATE_T__11_I_3;
   PIN ZN0 OUT T__11;
   PIN A0 IN GATE_T__11_N_1;
   PIN A1 IN GATE_T__11_N_2;
 END;
 SYM INV GATE_T__11_I_2;
   PIN ZN0 OUT GATE_T__11_N_2;
   PIN A0 IN T__147;
 END;
 SYM INV GATE_T__11_I_1;
   PIN ZN0 OUT GATE_T__11_N_1;
   PIN A0 IN T__146;
 END;
 SYM NAND2 GATE_T__12_I_3;
   PIN ZN0 OUT T__12;
   PIN A0 IN GATE_T__12_N_1;
   PIN A1 IN GATE_T__12_N_2;
 END;
 SYM INV GATE_T__12_I_2;
   PIN ZN0 OUT GATE_T__12_N_2;
   PIN A0 IN T__143;
 END;
 SYM INV GATE_T__12_I_1;
   PIN ZN0 OUT GATE_T__12_N_1;
   PIN A0 IN T__142;
 END;
 SYM NAND2 GATE_T__13_I_3;
   PIN ZN0 OUT T__13;
   PIN A0 IN GATE_T__13_N_1;
   PIN A1 IN GATE_T__13_N_2;
 END;
 SYM INV GATE_T__13_I_2;
   PIN ZN0 OUT GATE_T__13_N_2;
   PIN A0 IN T__145;
 END;
 SYM INV GATE_T__13_I_1;
   PIN ZN0 OUT GATE_T__13_N_1;
   PIN A0 IN T__144;
 END;
 SYM NAND2 GATE_T__14_I_3;
   PIN ZN0 OUT T__14;
   PIN A0 IN GATE_T__14_N_1;
   PIN A1 IN GATE_T__14_N_2;
 END;
 SYM INV GATE_T__14_I_2;
   PIN ZN0 OUT GATE_T__14_N_2;
   PIN A0 IN T__131;
 END;
 SYM INV GATE_T__14_I_1;
   PIN ZN0 OUT GATE_T__14_N_1;
   PIN A0 IN T__130;
 END;
 SYM NAND2 GATE_T__15_I_3;
   PIN ZN0 OUT T__15;
   PIN A0 IN GATE_T__15_N_1;
   PIN A1 IN GATE_T__15_N_2;
 END;
 SYM INV GATE_T__15_I_2;
   PIN ZN0 OUT GATE_T__15_N_2;
   PIN A0 IN T__137;
 END;
 SYM INV GATE_T__15_I_1;
   PIN ZN0 OUT GATE_T__15_N_1;
   PIN A0 IN T__136;
 END;
 SYM NAND2 GATE_T__16_I_3;
   PIN ZN0 OUT T__16;
   PIN A0 IN GATE_T__16_N_1;
   PIN A1 IN GATE_T__16_N_2;
 END;
 SYM INV GATE_T__16_I_2;
   PIN ZN0 OUT GATE_T__16_N_2;
   PIN A0 IN T__133;
 END;
 SYM INV GATE_T__16_I_1;
   PIN ZN0 OUT GATE_T__16_N_1;
   PIN A0 IN T__132;
 END;
 SYM NAND2 GATE_T__17_I_3;
   PIN ZN0 OUT T__17;
   PIN A0 IN GATE_T__17_N_1;
   PIN A1 IN GATE_T__17_N_2;
 END;
 SYM INV GATE_T__17_I_2;
   PIN ZN0 OUT GATE_T__17_N_2;
   PIN A0 IN T__135;
 END;
 SYM INV GATE_T__17_I_1;
   PIN ZN0 OUT GATE_T__17_N_1;
   PIN A0 IN T__134;
 END;
 SYM NAND2 GATE_T__18_I_3;
   PIN ZN0 OUT T__18;
   PIN A0 IN GATE_T__18_N_1;
   PIN A1 IN GATE_T__18_N_2;
 END;
 SYM INV GATE_T__18_I_2;
   PIN ZN0 OUT GATE_T__18_N_2;
   PIN A0 IN T__121;
 END;
 SYM INV GATE_T__18_I_1;
   PIN ZN0 OUT GATE_T__18_N_1;
   PIN A0 IN T__120;
 END;
 SYM NAND2 GATE_T__19_I_3;
   PIN ZN0 OUT T__19;
   PIN A0 IN GATE_T__19_N_1;
   PIN A1 IN GATE_T__19_N_2;
 END;
 SYM INV GATE_T__19_I_2;
   PIN ZN0 OUT GATE_T__19_N_2;
   PIN A0 IN T__127;
 END;
 SYM INV GATE_T__19_I_1;
   PIN ZN0 OUT GATE_T__19_N_1;
   PIN A0 IN T__126;
 END;
 SYM NAND2 GATE_T__20_I_3;
   PIN ZN0 OUT T__20;
   PIN A0 IN GATE_T__20_N_1;
   PIN A1 IN GATE_T__20_N_2;
 END;
 SYM INV GATE_T__20_I_2;
   PIN ZN0 OUT GATE_T__20_N_2;
   PIN A0 IN T__123;
 END;
 SYM INV GATE_T__20_I_1;
   PIN ZN0 OUT GATE_T__20_N_1;
   PIN A0 IN T__122;
 END;
 SYM NAND2 GATE_T__21_I_3;
   PIN ZN0 OUT T__21;
   PIN A0 IN GATE_T__21_N_1;
   PIN A1 IN GATE_T__21_N_2;
 END;
 SYM INV GATE_T__21_I_2;
   PIN ZN0 OUT GATE_T__21_N_2;
   PIN A0 IN T__125;
 END;
 SYM INV GATE_T__21_I_1;
   PIN ZN0 OUT GATE_T__21_N_1;
   PIN A0 IN T__124;
 END;
 SYM NAND2 GATE_T__22_I_3;
   PIN ZN0 OUT T__22;
   PIN A0 IN GATE_T__22_N_1;
   PIN A1 IN GATE_T__22_N_2;
 END;
 SYM INV GATE_T__22_I_2