pb.laf

VHDL实例,适合大家学习使用

 SYM NAND2 GATE_N_11_I_3;
   PIN ZN0 OUT N_11;
   PIN A0 IN GATE_N_11_N_1;
   PIN A1 IN GATE_N_11_N_2;
 END;
 SYM INV GATE_N_11_I_2;
   PIN ZN0 OUT GATE_N_11_N_2;
   PIN A0 IN T__119;
 END;
 SYM INV GATE_N_11_I_1;
   PIN ZN0 OUT GATE_N_11_N_1;
   PIN A0 IN T__118;
 END;
 SYM NAND2 GATE_N_12_I_3;
   PIN ZN0 OUT N_12;
   PIN A0 IN GATE_N_12_N_1;
   PIN A1 IN GATE_N_12_N_2;
 END;
 SYM INV GATE_N_12_I_2;
   PIN ZN0 OUT GATE_N_12_N_2;
   PIN A0 IN T__113;
 END;
 SYM INV GATE_N_12_I_1;
   PIN ZN0 OUT GATE_N_12_N_1;
   PIN A0 IN T__112;
 END;
 SYM NAND2 GATE_SEG1_I_3;
   PIN ZN0 OUT SEG1_COM_BLIF;
   PIN A0 IN I22_Q2_Q_BLIF;
   PIN A1 IN I22_Q1_Q_BLIF;
 END;
 SYM AND3 GATE_SEG2_I_4;
   PIN Z0 OUT SEG2_COM_BLIF;
   PIN A0 IN GATE_SEG2_N_1;
   PIN A1 IN GATE_SEG2_N_2;
   PIN A2 IN GATE_SEG2_N_3;
 END;
 SYM INV GATE_SEG2_I_3;
   PIN ZN0 OUT GATE_SEG2_N_3;
   PIN A0 IN I22_Q1_Q_BLIF;
 END;
 SYM INV GATE_SEG2_U3;
   PIN ZN0 OUT GATE_SEG2_N_2;
   PIN A0 IN I22_Q2_Q_BLIF;
 END;
 SYM INV GATE_SEG2_I_2;
   PIN ZN0 OUT GATE_SEG2_N_1;
   PIN A0 IN I22_Q0_Q_BLIF;
 END;
 SYM NAND2 GATE_SEG3_I_3;
   PIN ZN0 OUT SEG3_COM_BLIF;
   PIN A0 IN I22_Q2_Q_BLIF;
   PIN A1 IN I22_Q1_Q_BLIF;
 END;
 SYM NAND2 GATE_SEG4_I_3;
   PIN ZN0 OUT SEG4_COM_BLIF;
   PIN A0 IN I22_Q2_Q_BLIF;
   PIN A1 IN I22_Q1_Q_BLIF;
 END;
 SYM NAND2 GATE_SEG5_I_3;
   PIN ZN0 OUT SEG5_COM_BLIF;
   PIN A0 IN I22_Q2_Q_BLIF;
   PIN A1 IN I22_Q1_Q_BLIF;
 END;
 SYM NAND2 GATE_SEG6_I_3;
   PIN ZN0 OUT SEG6_COM_BLIF;
   PIN A0 IN I22_Q2_Q_BLIF;
   PIN A1 IN I22_Q1_Q_BLIF;
 END;
 SYM AND3 GATE_SEG7_I_4;
   PIN Z0 OUT SEG7_COM_BLIF;
   PIN A0 IN GATE_SEG7_N_1;
   PIN A1 IN GATE_SEG7_N_2;
   PIN A2 IN GATE_SEG7_N_3;
 END;
 SYM INV GATE_SEG7_I_3;
   PIN ZN0 OUT GATE_SEG7_N_3;
   PIN A0 IN I22_Q1_Q_BLIF;
 END;
 SYM INV GATE_SEG7_U3;
   PIN ZN0 OUT GATE_SEG7_N_2;
   PIN A0 IN I22_Q2_Q_BLIF;
 END;
 SYM INV GATE_SEG7_I_2;
   PIN ZN0 OUT GATE_SEG7_N_1;
   PIN A0 IN I22_Q0_Q_BLIF;
 END;
 SYM AND3 GATE_SEG8_I_4;
   PIN Z0 OUT SEG8_COM_BLIF;
   PIN A0 IN GATE_SEG8_N_1;
   PIN A1 IN GATE_SEG8_N_2;
   PIN A2 IN GATE_SEG8_N_3;
 END;
 SYM INV GATE_SEG8_I_3;
   PIN ZN0 OUT GATE_SEG8_N_3;
   PIN A0 IN I22_Q1_Q_BLIF;
 END;
 SYM INV GATE_SEG8_U3;
   PIN ZN0 OUT GATE_SEG8_N_2;
   PIN A0 IN I22_Q2_Q_BLIF;
 END;
 SYM INV GATE_SEG8_I_2;
   PIN ZN0 OUT GATE_SEG8_N_1;
   PIN A0 IN I22_Q0_Q_BLIF;
 END;
 SYM NAND2 GATE_N_13_D_REG_I_3;
   PIN ZN0 OUT N_13_D_REG;
   PIN A0 IN GATE_N_13_D_REG_N_1;
   PIN A1 IN GATE_N_13_D_REG_N_2;
 END;
 SYM INV GATE_N_13_D_REG_I_2;
   PIN ZN0 OUT GATE_N_13_D_REG_N_2;
   PIN A0 IN T__88;
 END;
 SYM INV GATE_N_13_D_REG_I_1;
   PIN ZN0 OUT GATE_N_13_D_REG_N_1;
   PIN A0 IN T__87;
 END;
 SYM XNOR2 GATE_N_14_D_REG_U1;
   PIN ZN0 OUT N_14_D_REG;
   PIN A0 IN N_14_Q_BLIF;
   PIN A1 IN T__25;
 END;
 SYM NAND2 GATE_N_15_D_REG_I_3;
   PIN ZN0 OUT N_15_D_REG;
   PIN A0 IN GATE_N_15_D_REG_N_1;
   PIN A1 IN GATE_N_15_D_REG_N_2;
 END;
 SYM INV GATE_N_15_D_REG_I_2;
   PIN ZN0 OUT GATE_N_15_D_REG_N_2;
   PIN A0 IN T__86;
 END;
 SYM INV GATE_N_15_D_REG_I_1;
   PIN ZN0 OUT GATE_N_15_D_REG_N_1;
   PIN A0 IN T__85;
 END;
 SYM LXOR2 GATE_N_16_D_REG_U1;
   PIN Z0 OUT N_16_D_REG;
   PIN A0 IN N_36_Q_BLIF;
   PIN A1 IN N_16_Q_BLIF;
 END;
 SYM NAND2 GATE_N_17_D_REG_I_3;
   PIN ZN0 OUT N_17_D_REG;
   PIN A0 IN GATE_N_17_D_REG_N_1;
   PIN A1 IN GATE_N_17_D_REG_N_2;
 END;
 SYM INV GATE_N_17_D_REG_I_2;
   PIN ZN0 OUT GATE_N_17_D_REG_N_2;
   PIN A0 IN T__82;
 END;
 SYM INV GATE_N_17_D_REG_I_1;
   PIN ZN0 OUT GATE_N_17_D_REG_N_1;
   PIN A0 IN T__81;
 END;
 SYM XNOR2 GATE_N_18_D_REG_U1;
   PIN ZN0 OUT N_18_D_REG;
   PIN A0 IN N_18_Q_BLIF;
   PIN A1 IN T__29;
 END;
 SYM NAND2 GATE_N_19_D_REG_I_3;
   PIN ZN0 OUT N_19_D_REG;
   PIN A0 IN GATE_N_19_D_REG_N_1;
   PIN A1 IN GATE_N_19_D_REG_N_2;
 END;
 SYM INV GATE_N_19_D_REG_I_2;
   PIN ZN0 OUT GATE_N_19_D_REG_N_2;
   PIN A0 IN T__80;
 END;
 SYM INV GATE_N_19_D_REG_I_1;
   PIN ZN0 OUT GATE_N_19_D_REG_N_1;
   PIN A0 IN T__79;
 END;
 SYM LXOR2 GATE_N_20_D_REG_U1;
   PIN Z0 OUT N_20_D_REG;
   PIN A0 IN N_36_Q_BLIF;
   PIN A1 IN N_20_Q_BLIF;
 END;
 SYM NAND2 GATE_N_21_D_REG_I_3;
   PIN ZN0 OUT N_21_D_REG;
   PIN A0 IN GATE_N_21_D_REG_N_1;
   PIN A1 IN GATE_N_21_D_REG_N_2;
 END;
 SYM INV GATE_N_21_D_REG_I_2;
   PIN ZN0 OUT GATE_N_21_D_REG_N_2;
   PIN A0 IN T__78;
 END;
 SYM INV GATE_N_21_D_REG_I_1;
   PIN ZN0 OUT GATE_N_21_D_REG_N_1;
   PIN A0 IN T__77;
 END;
 SYM NAND2 GATE_N_22_D_REG_I_3;
   PIN ZN0 OUT N_22_D_REG;
   PIN A0 IN GATE_N_22_D_REG_N_1;
   PIN A1 IN GATE_N_22_D_REG_N_2;
 END;
 SYM INV GATE_N_22_D_REG_I_2;
   PIN ZN0 OUT GATE_N_22_D_REG_N_2;
   PIN A0 IN T__76;
 END;
 SYM INV GATE_N_22_D_REG_I_1;
   PIN ZN0 OUT GATE_N_22_D_REG_N_1;
   PIN A0 IN T__75;
 END;
 SYM LXOR2 GATE_N_23_D_REG_U1;
   PIN Z0 OUT N_23_D_REG;
   PIN A0 IN N_23_Q_BLIF;
   PIN A1 IN I23_N_4;
 END;
 SYM NAND2 GATE_N_24_D_REG_I_3;
   PIN ZN0 OUT N_24_D_REG;
   PIN A0 IN GATE_N_24_D_REG_N_1;
   PIN A1 IN GATE_N_24_D_REG_N_2;
 END;
 SYM INV GATE_N_24_D_REG_I_2;
   PIN ZN0 OUT GATE_N_24_D_REG_N_2;
   PIN A0 IN T__72;
 END;
 SYM INV GATE_N_24_D_REG_I_1;
   PIN ZN0 OUT GATE_N_24_D_REG_N_1;
   PIN A0 IN T__71;
 END;
 SYM XNOR2 GATE_N_25_D_REG_U1;
   PIN ZN0 OUT N_25_D_REG;
   PIN A0 IN N_25_Q_BLIF;
   PIN A1 IN T__35;
 END;
 SYM NAND2 GATE_N_26_D_REG_I_3;
   PIN ZN0 OUT N_26_D_REG;
   PIN A0 IN GATE_N_26_D_REG_N_1;
   PIN A1 IN GATE_N_26_D_REG_N_2;
 END;
 SYM INV GATE_N_26_D_REG_I_2;
   PIN ZN0 OUT GATE_N_26_D_REG_N_2;
   PIN A0 IN T__70;
 END;
 SYM INV GATE_N_26_D_REG_I_1;
   PIN ZN0 OUT GATE_N_26_D_REG_N_1;
   PIN A0 IN T__69;
 END;
 SYM LXOR2 GATE_N_27_D_REG_U1;
   PIN Z0 OUT N_27_D_REG;
   PIN A0 IN N_36_Q_BLIF;
   PIN A1 IN N_27_Q_BLIF;
 END;
 SYM NAND2 GATE_N_28_D_REG_I_3;
   PIN ZN0 OUT N_28_D_REG;
   PIN A0 IN GATE_N_28_D_REG_N_1;
   PIN A1 IN GATE_N_28_D_REG_N_2;
 END;
 SYM INV GATE_N_28_D_REG_I_2;
   PIN ZN0 OUT GATE_N_28_D_REG_N_2;
   PIN A0 IN T__68;
 END;
 SYM INV GATE_N_28_D_REG_I_1;
   PIN ZN0 OUT GATE_N_28_D_REG_N_1;
   PIN A0 IN T__67;
 END;
 SYM NAND2 GATE_N_29_D_REG_I_3;
   PIN ZN0 OUT N_29_D_REG;
   PIN A0 IN GATE_N_29_D_REG_N_1;
   PIN A1 IN GATE_N_29_D_REG_N_2;
 END;
 SYM INV GATE_N_29_D_REG_I_2;
   PIN ZN0 OUT GATE_N_29_D_REG_N_2;
   PIN A0 IN T__66;
 END;
 SYM INV GATE_N_29_D_REG_I_1;
   PIN ZN0 OUT GATE_N_29_D_REG_N_1;
   PIN A0 IN T__65;
 END;
 SYM LXOR2 GATE_N_30_D_REG_U1;
   PIN Z0 OUT N_30_D_REG;
   PIN A0 IN N_30_Q_BLIF;
   PIN A1 IN I23_N_2;
 END;
 SYM NAND2 GATE_N_31_D_REG_I_3;
   PIN ZN0 OUT N_31_D_REG;
   PIN A0 IN GATE_N_31_D_REG_N_1;
   PIN A1 IN GATE_N_31_D_REG_N_2;
 END;
 SYM INV GATE_N_31_D_REG_I_2;
   PIN ZN0 OUT GATE_N_31_D_REG_N_2;
   PIN A0 IN T__62;
 END;
 SYM INV GATE_N_31_D_REG_I_1;
   PIN ZN0 OUT GATE_N_31_D_REG_N_1;
   PIN A0 IN T__61;
 END;
 SYM XNOR2 GATE_N_32_D_REG_U1;
   PIN ZN0 OUT N_32_D_REG;
   PIN A0 IN N_32_Q_BLIF;
   PIN A1 IN T__41;
 END;
 SYM NAND2 GATE_N_33_D_REG_I_3;
   PIN ZN0 OUT N_33_D_REG;
   PIN A0 IN GATE_N_33_D_REG_N_1;
   PIN A1 IN GATE_N_33_D_REG_N_2;
 END;
 SYM INV GATE_N_33_D_REG_I_2;
   PIN ZN0 OUT GATE_N_33_D_REG_N_2;
   PIN A0 IN T__60;
 END;
 SYM INV GATE_N_33_D_REG_I_1;
   PIN ZN0 OUT GATE_N_33_D_REG_N_1;
   PIN A0 IN T__59;
 END;
 SYM LXOR2 GATE_N_34_D_REG_U1;
   PIN Z0 OUT N_34_D_REG;
   PIN A0 IN N_36_Q_BLIF;
   PIN A1 IN N_34_Q_BLIF;
 END;
 SYM INV GATE_N_36_D_REG_I_1;
   PIN ZN0 OUT N_36_D_REG;
   PIN A0 IN N_36_Q_BLIF;
 END;
 SYM NAND2 GATE_I26_Q1_D_REG_I_3;
   PIN ZN0 OUT I26_Q1_D_REG;
   PIN A0 IN GATE_I26_Q1_D_REG_N_1;
   PIN A1 IN GATE_I26_Q1_D_REG_N_2;
 END;
 SYM INV GATE_I26_Q1_D_REG_I_2;
   PIN ZN0 OUT GATE_I26_Q1_D_REG_N_2;
   PIN A0 IN T__58;
 END;
 SYM INV GATE_I26_Q1_D_REG_I_1;