pb.laf

VHDL实例,适合大家学习使用

 SYM FD21 FF_N_32_U1  ;
   PIN Q0 OUT N_32_Q_BLIF;
   PIN CD IN N_32_AR;
   PIN CLK IN N_32_C;
   PIN D0 IN N_32_D_REG;
 END;
 SYM FD21 FF_N_33_U1  ;
   PIN Q0 OUT N_33_Q_BLIF;
   PIN CD IN N_33_AR;
   PIN CLK IN N_33_C;
   PIN D0 IN N_33_D_REG;
 END;
 SYM FD21 FF_N_34_U1  ;
   PIN Q0 OUT N_34_Q_BLIF;
   PIN CD IN N_34_AR;
   PIN CLK IN N_34_C;
   PIN D0 IN N_34_D_REG;
 END;
 SYM FD21 FF_N_36_U1  ;
   PIN Q0 OUT N_36_Q_BLIF;
   PIN CD IN IN_CLK_U1_Z0;
   PIN CLK IN IN_CLK_U1_Z0;
   PIN D0 IN N_36_D_REG;
 END;
 SYM FD21 FF_I26_Q1_U1  ;
   PIN Q0 OUT I26_Q1_Q_BLIF;
   PIN CD IN IN_CLK_U1_Z0;
   PIN CLK IN IN_CLK_U1_Z0;
   PIN D0 IN I26_Q1_D_REG;
 END;
 SYM FD21 FF_I26_Q2_U1  ;
   PIN Q0 OUT I26_Q2_Q_BLIF;
   PIN CD IN IN_CLK_U1_Z0;
   PIN CLK IN IN_CLK_U1_Z0;
   PIN D0 IN I26_Q2_D_REG;
 END;
 SYM FD21 FF_I26_Q3_U1  ;
   PIN Q0 OUT I26_Q3_Q_BLIF;
   PIN CD IN IN_CLK_U1_Z0;
   PIN CLK IN IN_CLK_U1_Z0;
   PIN D0 IN I26_Q3_D_REG;
 END;
 SYM FD11 FF_I25_SS1_U1  ;
   PIN Q0 OUT I25_SS1_Q_BLIF;
   PIN CLK IN N_36_Q_BLIF;
   PIN D0 IN I25_SS1_D_REG;
 END;
 SYM FD11 FF_I25_SS0_U1  ;
   PIN Q0 OUT I25_SS0_Q_BLIF;
   PIN CLK IN N_36_Q_BLIF;
   PIN D0 IN I25_SS0_D_REG;
 END;
 SYM FD11 FF_I22_Q2_U1  ;
   PIN Q0 OUT I22_Q2_Q_BLIF;
   PIN CLK IN IN_CLK_U1_Z0;
   PIN D0 IN I22_Q2_D_REG;
 END;
 SYM FD11 FF_I22_Q1_U1  ;
   PIN Q0 OUT I22_Q1_Q_BLIF;
   PIN CLK IN IN_CLK_U1_Z0;
   PIN D0 IN I22_Q1_D_REG;
 END;
 SYM FD11 FF_I22_Q0_U1  ;
   PIN Q0 OUT I22_Q0_Q_BLIF;
   PIN CLK IN IN_CLK_U1_Z0;
   PIN D0 IN I22_Q0_D_REG;
 END;
 SYM NAND2 GATE_a_I_3;
   PIN ZN0 OUT A_COM_BLIF;
   PIN A0 IN GATE_A_N_1;
   PIN A1 IN GATE_A_N_2;
 END;
 SYM INV GATE_a_I_2;
   PIN ZN0 OUT GATE_A_N_2;
   PIN A0 IN T__109;
 END;
 SYM INV GATE_a_I_1;
   PIN ZN0 OUT GATE_A_N_1;
   PIN A0 IN T__108;
 END;
 SYM NAND2 GATE_b_I_3;
   PIN ZN0 OUT B_COM_BLIF;
   PIN A0 IN GATE_B_N_1;
   PIN A1 IN GATE_B_N_2;
 END;
 SYM INV GATE_b_I_2;
   PIN ZN0 OUT GATE_B_N_2;
   PIN A0 IN T__107;
 END;
 SYM INV GATE_b_I_1;
   PIN ZN0 OUT GATE_B_N_1;
   PIN A0 IN T__106;
 END;
 SYM NAND2 GATE_c_I_3;
   PIN ZN0 OUT C_COM_BLIF;
   PIN A0 IN GATE_C_N_1;
   PIN A1 IN GATE_C_N_2;
 END;
 SYM INV GATE_c_I_2;
   PIN ZN0 OUT GATE_C_N_2;
   PIN A0 IN T__103;
 END;
 SYM INV GATE_c_I_1;
   PIN ZN0 OUT GATE_C_N_1;
   PIN A0 IN T__102;
 END;
 SYM NAND3 GATE_d_I_1;
   PIN ZN0 OUT D_COM_BLIF;
   PIN A0 IN GATE_D_N_1;
   PIN A1 IN GATE_D_N_2;
   PIN A2 IN GATE_D_N_3;
 END;
 SYM INV GATE_d_I_3;
   PIN ZN0 OUT GATE_D_N_3;
   PIN A0 IN T__100;
 END;
 SYM INV GATE_d_U3;
   PIN ZN0 OUT GATE_D_N_2;
   PIN A0 IN T__99;
 END;
 SYM INV GATE_d_I_2;
   PIN ZN0 OUT GATE_D_N_1;
   PIN A0 IN T__101;
 END;
 SYM INV GATE_e_I_1;
   PIN ZN0 OUT GATE_E_N_1;
   PIN A0 IN N_12;
 END;
 SYM AND2 GATE_e_U1;
   PIN Z0 OUT E_COM_BLIF;
   PIN A0 IN GATE_E_N_1;
   PIN A1 IN T__5;
 END;
 SYM NAND2 GATE_f_I_3;
   PIN ZN0 OUT F_COM_BLIF;
   PIN A0 IN GATE_F_N_1;
   PIN A1 IN GATE_F_N_2;
 END;
 SYM INV GATE_f_I_2;
   PIN ZN0 OUT GATE_F_N_2;
   PIN A0 IN T__96;
 END;
 SYM INV GATE_f_I_1;
   PIN ZN0 OUT GATE_F_N_1;
   PIN A0 IN T__95;
 END;
 SYM NAND2 GATE_g_I_3;
   PIN ZN0 OUT G_COM_BLIF;
   PIN A0 IN GATE_G_N_1;
   PIN A1 IN GATE_G_N_2;
 END;
 SYM INV GATE_g_I_2;
   PIN ZN0 OUT GATE_G_N_2;
   PIN A0 IN T__92;
 END;
 SYM INV GATE_g_I_1;
   PIN ZN0 OUT GATE_G_N_1;
   PIN A0 IN T__91;
 END;
 SYM INV GATE_N_27_AR_I_1;
   PIN ZN0 OUT N_27_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_27_C_I_1;
   PIN ZN0 OUT N_27_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_26_AR_I_1;
   PIN ZN0 OUT N_26_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_26_C_I_1;
   PIN ZN0 OUT N_26_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_25_AR_I_1;
   PIN ZN0 OUT N_25_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_25_C_I_1;
   PIN ZN0 OUT N_25_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_24_AR_I_1;
   PIN ZN0 OUT N_24_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_24_C_I_1;
   PIN ZN0 OUT N_24_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_34_AR_I_1;
   PIN ZN0 OUT N_34_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_34_C_I_1;
   PIN ZN0 OUT N_34_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_33_AR_I_1;
   PIN ZN0 OUT N_33_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_33_C_I_1;
   PIN ZN0 OUT N_33_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_32_AR_I_1;
   PIN ZN0 OUT N_32_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_32_C_I_1;
   PIN ZN0 OUT N_32_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_31_AR_I_1;
   PIN ZN0 OUT N_31_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_31_C_I_1;
   PIN ZN0 OUT N_31_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_20_AR_I_1;
   PIN ZN0 OUT N_20_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_20_C_I_1;
   PIN ZN0 OUT N_20_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_19_AR_I_1;
   PIN ZN0 OUT N_19_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_19_C_I_1;
   PIN ZN0 OUT N_19_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_18_AR_I_1;
   PIN ZN0 OUT N_18_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_18_C_I_1;
   PIN ZN0 OUT N_18_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_17_AR_I_1;
   PIN ZN0 OUT N_17_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_17_C_I_1;
   PIN ZN0 OUT N_17_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_16_AR_I_1;
   PIN ZN0 OUT N_16_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_16_C_I_1;
   PIN ZN0 OUT N_16_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_15_AR_I_1;
   PIN ZN0 OUT N_15_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_15_C_I_1;
   PIN ZN0 OUT N_15_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_14_AR_I_1;
   PIN ZN0 OUT N_14_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_14_C_I_1;
   PIN ZN0 OUT N_14_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_13_AR_I_1;
   PIN ZN0 OUT N_13_AR;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM INV GATE_N_13_C_I_1;
   PIN ZN0 OUT N_13_C;
   PIN A0 IN IN_CLR_U1_Z0;
 END;
 SYM AND3 GATE_I23_N_2_I_4;
   PIN Z0 OUT I23_N_2;
   PIN A0 IN T__152;
   PIN A1 IN N_36_Q_BLIF;
   PIN A2 IN T__153;
 END;
 SYM AND3 GATE_I23_N_4_I_4;
   PIN Z0 OUT I23_N_4;
   PIN A0 IN T__156;
   PIN A1 IN N_36_Q_BLIF;
   PIN A2 IN T__157;
 END;
 SYM NAND2 GATE_N_9_I_3;
   PIN ZN0 OUT N_9;
   PIN A0 IN GATE_N_9_N_1;
   PIN A1 IN GATE_N_9_N_2;
 END;
 SYM INV GATE_N_9_I_2;
   PIN ZN0 OUT GATE_N_9_N_2;
   PIN A0 IN T__139;
 END;
 SYM INV GATE_N_9_I_1;
   PIN ZN0 OUT GATE_N_9_N_1;
   PIN A0 IN T__138;
 END;
 SYM NAND2 GATE_N_10_I_3;
   PIN ZN0 OUT N_10;
   PIN A0 IN GATE_N_10_N_1;
   PIN A1 IN GATE_N_10_N_2;
 END;
 SYM INV GATE_N_10_I_2;
   PIN ZN0 OUT GATE_N_10_N_2;
   PIN A0 IN T__129;
 END;
 SYM INV GATE_N_10_I_1;
   PIN ZN0 OUT GATE_N_10_N_1;
   PIN A0 IN T__128;
 END;