cdt6.abt

VHDL实例,适合大家学习使用

MODULE cdt6

" TOOL:     ispDesignEXPERT
" DATE:     Wed Feb 27 10:39:16 2002 
" TITLE:    
" MODULE:   cdt6
" DESIGN:   cdt6
" FILENAME: CDT6.abt
" PROJECT:  pb
" VERSION:  8.4

" NOTE: DO NOT EDIT THIS FILE DIRECTLY.
" This file is auto generated by ispDesignEXPERT System.
" It can be removed or overwritten automatically.
" If you want to edit this file, copy it to another file or 
" rename it with different file extension first. 


" Inputs
    EN pin;
    CLR pin;
    CLK pin;


" Outputs
    Q2 pin;
    Q1 pin;
    Q0 pin;
    CY pin;


" Bidirs



Test_vectors
([EN,CLR,CLK] -> [Q2,Q1,Q0,CY])


END