pb.ldb

VHDL实例,适合大家学习使用

DESIGN pbch
{
    PORT CLK input 
    {
        ATTR LOCK string 2
15

        {

        }

    }
    PORT CLR input 
    {
        ATTR LOCK string 2
16

        {

        }

    }
    PORT KEY input 
    {
        ATTR LOCK string 2
17

        {

        }

    }
    PORT SEG1 output 
    {

    }
    PORT SEG2 output 
    {

    }
    PORT SEG3 output 
    {

    }
    PORT SEG4 output 
    {

    }
    PORT SEG5 output 
    {

    }
    PORT SEG6 output 
    {

    }
    PORT SEG7 output 
    {

    }
    PORT SEG8 output 
    {

    }
    PORT a output 
    {

    }
    PORT b output 
    {

    }
    PORT c output 
    {

    }
    PORT d output 
    {

    }
    PORT e output 
    {

    }
    PORT f output 
    {

    }
    PORT g output 
    {

    }
    PORT dt output 
    {

    }
    ATTR CONFIGURATION string 13
CONFIG_HOLDER

    {
        ATTR $default string 1755
CFG_LST=$default
	VERSION=1.00
	OPTION=
	DEVICE=ispLSI1032E-70LJ84
	RESERVED_PINS=
	TIMING_ANALYSIS=0
	TA_MIN_DELAY=1
	TA_LSPATHS=1
	TA_MAX_PATHS=10
	TA_DEST_NODES=0
	TA_CLK_FREQ=ON
	TA_SETUP_HOLD=ON
	TA_CLK_TO_OUT=ON
	TA_TPD=ON
	TA_ENUM_PATHS=1
	TIMING_FILE=
	PARAMETER_FILE=
	USE_PARAMETER_FILE=OFF
	PERFORM_TA=ON
	PIN_FILE=
	PART_NAME=
	OUTPUT_FORM=
	EXTENDED_ROUTE=ON
	IGNORE_FIXED_PIN=OFF
	USE_GLOBAL_RESET=ON
	EXTENDED_LOGIC_OPT=OFF
	MIN_GLB=1
	CARRY_PIN_DIR=OFF
	CASE_SENSITIVE=OFF
	IGNORE_RESERVE_PIN=OFF
	SECURITY=OFF
	ISP=ON
	ISP_EXCEPT_Y2=OFF
	Y1_AS_RESET=OFF
	PULLUP=ON
	SLOWSLEW=OFF
	OPENDRAIN=OFF
	PORT_LST
		CLK	D=IN	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		CLR	D=IN	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		KEY	D=IN	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		SEG1	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		SEG2	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		SEG3	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		SEG4	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		SEG5	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		SEG6	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		SEG7	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		SEG8	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		a	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		b	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		c	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		d	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		dt	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		e	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		f	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
		g	D=OUT	L=	P=ON	S=OFF	C=OFF	O=OFF	DLY=OFF	V=VCCIO	
	PORT_END

	OPTION_LST
		EFFORT=2
		STRATEGY=d
		MAX_GLB_IN=16
		MAX_GLB_OUT=4
	OPTION_END
CFG_END


        {

        }

    }
    ATTR PART string 18
ispLSI1032E-70LJ84

    {

    }
    ATTR TECHNOLOGY string 4
pLSI

    {

    }
    ATTR STAT string 33
edif2laf 1.0 27.2.2002 12.21.12 1

    {

    }
    ATTR DESIGN string 4
pbch

    {

    }
    ATTR DESIGN_REV string 3
0.0

    {

    }

}