key.vht

VHDL实例,适合大家学习使用

-- VHDL Test Bench Created from source file key.vhd -- Wed Feb 27 10:40:07 2002
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Lattice recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "source->import"
-- menu in the ispDesignExpert System Project Navigator to import the testbench.
-- Then edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT key
	PORT(
		K : IN std_logic;
		CLK : IN std_logic;          
		SS1 : OUT std_logic;
		SS0 : OUT std_logic;
		EN : OUT std_logic
		);
	END COMPONENT;

	SIGNAL SS1 :  std_logic;
	SIGNAL SS0 :  std_logic;
	SIGNAL K :  std_logic;
	SIGNAL EN :  std_logic;
	SIGNAL CLK :  std_logic;

BEGIN

	uut: key PORT MAP(
		SS1 => SS1,
		SS0 => SS0,
		K => K,
		EN => EN,
		CLK => CLK
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;