pbch.bl1

VHDL实例,适合大家学习使用

#$ TOOL ispDesignEXPERT 8.4
#$ DATE Wed Feb 27 11:38:01 2002
#$ TITLE pbch.bls 
#$ PROPERTY PLSI PULLUP ON
#$ PROPERTY PLSI LOCK KEY 17
#$ PROPERTY PLSI LOCK CLR 16
#$ PROPERTY PLSI LOCK CLK 15
#$ MODULE pbch
#$ PINS 19 KEY'ke'  CLR'ke'  CLK'ke'  dt'o'  g'o'  f'o'  e'o'  d'o'  c'o'  b'o'  a'o'  SEG8'o'  SEG7'o'  SEG6'o'  SEG5'o'  SEG4'o'  SEG3'o'  SEG2'o'  SEG1'o' 
#$ NODES 54 N_49 N_50'o'  N_41 N_42 N_43 N_44 N_45 N_46 N_47 N_48 N_1 N_2 N_3 N_4 N_5 N_6 N_7 N_8 N_9 N_10 N_11 N_12 N_13 N_14 N_15 N_16 N_17 N_18 N_19 N_20 N_21 N_22 N_23 \
#  N_24 N_25 N_26 N_27 N_28 N_29 N_30 N_31 N_32 N_33 N_34 N_36 VCC GND N_37'o'  N_38'o'  N_39'o'  I26>CY I26>Q1 I26>Q2 I26>Q3
#$ INTERFACE bc07  12 D0'i'  D1'i'  D2'i'  D3'i'  a'o'  b'o'  c'o'  d'o'  dt'o'  e'o'  f'o'  g'o' 
#$ INTERFACE cdt10  8 CLK'i'  CLR'i'  EN'i'  CY'o'  Q0'o'  Q1'o'  Q2'o'  Q3'o' 
#$ INTERFACE cout  25 CLK'i'  CLR'i'  EN'i'  B0'o'  B1'o'  B2'o'  B3'o'  B4'o'  B5'o'  B6'o'  M0'o'  M1'o'  M2'o'  M3'o'  M4'o'  M5'o'  M6'o'  MB0'o'  MB1'o'  MB2'o'  MB3'o'  MB4'o'  MB5'o'  MB6'o'  MB7'o' 
#$ INTERFACE key  3 CLK'i'  K'i'  EN'o' 
#$ INTERFACE nulx  35 CLK'i'  M0'i'  M1'i'  M2'i'  M3'i'  M4'i'  M5'i'  M6'i'  MS0'i'  MS1'i'  MS2'i'  MS3'i'  MS4'i'  MS5'i'  MS6'i'  MS7'i'  S0'i'  S1'i'  S2'i'  S3'i'  S4'i'  S5'i'  S6'i'  OUT0'o'  OUT1'o'  OUT2'o'  OUT3'o'  SEG1'o'  SEG2'o'  SEG3'o'  SEG4'o'  SEG5'o'  SEG6'o'  SEG7'o'  SEG8'o' 
#$ INSTANCE I21 bc07 12 N_9 N_10 N_11 N_12 N_4 N_5 N_6 N_7 N_1 N_8 N_3 N_2
#$ INSTANCE I26 cdt10 8 N_37 GND VCC I26>CY N_36 I26>Q1 I26>Q2 I26>Q3
#$ INSTANCE I23 cout 25 N_36 N_38 N_49 N_27 N_26 N_25 N_24 N_23 N_22 N_21 N_34 N_33 N_32 N_31 N_30 N_29 N_28 N_20 N_19 N_18 N_17 N_16 N_15 N_14 N_13
#$ INSTANCE I25 key 3 N_36 N_50 N_49
#$ INSTANCE I22 nulx 35 N_37 N_34 N_33 N_32 N_31 N_30 N_29 N_28 N_20 N_19 N_18 N_17 N_16 N_15 N_14 N_13 N_27 N_26 N_25 N_24 N_23 N_22 N_21 N_9 N_10 N_11 N_12 N_48 N_47 \
#  N_46 N_45 N_44 N_43 N_42 N_41

.model pbch
.inputs CLK.BLIF CLR.BLIF KEY.BLIF N_39.BLIF N_1.BLIF N_2.BLIF N_3.BLIF N_8.BLIF \
N_7.BLIF N_6.BLIF N_5.BLIF N_4.BLIF N_41.BLIF N_42.BLIF N_43.BLIF N_44.BLIF \
N_45.BLIF N_46.BLIF N_47.BLIF N_48.BLIF
.outputs VCC GND N_37 N_39 N_50 N_38 dt g f e d c b a SEG8 SEG7 SEG6 SEG5 SEG4 \
SEG3 SEG2 SEG1
.names VCC
 1
.names GND
.names N_39.BLIF N_38
0 1
1 0
.names CLK.BLIF N_37
1 1
0 0
.names CLR.BLIF N_39
1 1
0 0
.names KEY.BLIF N_50
1 1
0 0
.names N_1.BLIF dt
1 1
0 0
.names N_2.BLIF g
1 1
0 0
.names N_3.BLIF f
1 1
0 0
.names N_8.BLIF e
1 1
0 0
.names N_7.BLIF d
1 1
0 0
.names N_6.BLIF c
1 1
0 0
.names N_5.BLIF b
1 1
0 0
.names N_4.BLIF a
1 1
0 0
.names N_41.BLIF SEG8
1 1
0 0
.names N_42.BLIF SEG7
1 1
0 0
.names N_43.BLIF SEG6
1 1
0 0
.names N_44.BLIF SEG5
1 1
0 0
.names N_45.BLIF SEG4
1 1
0 0
.names N_46.BLIF SEG3
1 1
0 0
.names N_47.BLIF SEG2
1 1
0 0
.names N_48.BLIF SEG1
1 1
0 0
.end