pb.log

VHDL实例,适合大家学习使用

ispEXPERT Compiler Release 8.4.06.39, Nov  9 2000 13:09:01

Copyright (C) 1994-2000 by Lattice Semiconductor Corporation.
All Rights Reserved.


Design Process Management 

Renaming existing log file to pb.lo-
Renaming existing rpt file to pb.rp-

Preprocessing design 'pb'...

Processing design 'pb'...


Logical LAF Reading and Translation 
  
Reading file 'pb.laf'... 
32579 WARNING: Pin 'CLK' is locked to '15' in design but no pin locking 
      in external pin file; Pin lock is ignored 
32579 WARNING: Pin 'CLR' is locked to '16' in design but no pin locking 
      in external pin file; Pin lock is ignored 
32579 WARNING: Pin 'KEY' is locked to '17' in design but no pin locking 
      in external pin file; Pin lock is ignored 
  
Checking design rules... 
Selected part is 'ispLSI1032E-70LJ84' 
  
Writing output files... 
  
Logical LAF reading and translation completed successfully 


Synthesis and Partitioning 
  
Reading design 'pb'... 
  
Optimizing logic... 
33581 WARNING: Register 'FF_I25_SS0_U1' is not observable from any 
      output pin; register is removed 
33581 WARNING: Register 'FF_I25_SS1_U1' is not observable from any 
      output pin; register is removed 
33581 WARNING: Register 'FF_I26_Q1_U1' is not observable from any output
      pin; register is removed 
33581 WARNING: Register 'FF_I26_Q2_U1' is not observable from any output
      pin; register is removed 
33581 WARNING: Register 'FF_I26_Q3_U1' is not observable from any output
      pin; register is removed 
33612 WARNING: Input pin 'KEY' is not used; pin is removed 
  
Trying to move PT reset signal to global reset pin... 
      PT reset signal cannot be moved to global reset pin 
      In order to move PT reset signal to global reset pin, the 
      following conditions need to be satisfied: 
      1. There exists at least one pin which drives all register's reset
      signals 
      2. This pin is unlocked 
      3. This pin does not drive any data signals 
      4. This pin can be disjointly decomposed with other pins, if any, 
      which drive reset signals 
  
Partitioning logic into 16-input, 16-input with DIs, functions to 
      minimize delay... 
  
Extracting LXOR2 gates to minimize delay... 
  
Packing functions into GLBs using 16 inputs and 4 outputs per GLB to 
      minimize delay... 
Constant VCC drives pin 'DT' 
  
Synthesis and partitioning statistics: 
  
Number of Macrocells is 41 
Number of GLBs is 12 
Number of product terms is 178 
Maximum number of GLB levels is 2 
Average number of inputs per GLB is 11.2 
Average number of outputs per GLB is 3.4 
Average number of product terms per GLB is 14.8 
  
Synthesis and partitioning completed successfully 


Physical LAF Reading and Translation

Reading design 'pb'...

Writing output files...

Physical LAF reading and translation completed successfully


Placement and Routing

Reading design 'pb'...

Routing


Writing output files...

Placement and routing completed successfully


Technology Remapping 
  
Reading design 'pb'... 
  
Remapping... 
  
Writing output files... 
  
Technology remapping completed successfully 


Physical LAF Reading and Translation

Reading design 'pb'...

Writing output files...

Physical LAF reading and translation completed successfully


Fusemap Generation

Reading design 'pb'...

Writing output files...

Fusemap generation completed successfully


Simulation LAF Netlist Generation

Reading design 'pb'...

Writing output files...


Information: Global reset (XRESET) is generated to reset all registers



Simulation LAF netlist generation completed successfully


Timing Analyzer 
Reading design pb .... 

Evaluating maximum operating frequency...
Evaluating setup and hold times...
43006 WARNING: No chip input pins drive data input and clock input of any register

Calculating  Tpd Path delays ...

Calculating  Tco Path delays ...

....................................................................              


Timing analyzer completed successfully 
Node Observability Analyzer Software Version 8.4.06.39.00, Aug 17 2000 
      03:22:20 
  
Copyright (C) 1999-2000 by Lattice Semiconductor Corporation. 
All Rights Reserved. 
  
Reading design 'pb'... 
  
Writing output files... 
  
Node Observability Analyzer completed successfully 


Design process management completed successfully