keyb.abl

VHDL实例,适合大家学习使用

MODULE KEY
CLK,K   PIN;
EN      PIN;
SS1,SS0 PIN ISTYPE 'REG';
SS = [SS1,SS0];
S0 = ^B00;S1 = ^B01;S2 = ^B10;S3 = ^B11;
EQUATIONS
SS.CLK = CLK;

STATE_DIAGRAM SS
  STATE S0:EN = 0;
        CASE K==1:S0;
             K==0:S1;
        ENDCASE

  STATE S1:EN = 1;
        CASE K==0:S1;
             K==1:S2;
        ENDCASE

  STATE S2:EN = 1;
        CASE K==0:S2;
             K==1:S3;
        ENDCASE

  STATE S3:EN = 0;
        CASE K==0:S3;
             K==1:S0;
        ENDCASE
END