pb.mod

VHDL实例,适合大家学习使用

MODEL
MODEL_VERSION "1.0";
DESIGN "pb";
DATE "Wed Feb 27 11:35:55 2002";
VENDOR "Lattice Semiconductor Co. Ltd.";
PROGRAM "STAMP Model Generator";

/* port name and type */
INPUT KEY;
INPUT XRESET;
INPUT CLK;
OUTPUT A;
OUTPUT B;
OUTPUT C;
OUTPUT D;
OUTPUT E;
OUTPUT F;
OUTPUT G;
OUTPUT SEG1;
OUTPUT DT;
OUTPUT SEG2;
OUTPUT SEG3;
OUTPUT SEG4;
OUTPUT SEG5;
OUTPUT SEG6;
OUTPUT SEG7;
OUTPUT SEG8;

/* timing arc definitions */
KEY_E_delay: DELAY KEY E;
CLK_SEG8_delay: DELAY CLK SEG8;
CLK_SEG7_delay: DELAY CLK SEG7;
CLK_SEG6_delay: DELAY CLK SEG6;
CLK_SEG5_delay: DELAY CLK SEG5;
CLK_SEG4_delay: DELAY CLK SEG4;
CLK_SEG3_delay: DELAY CLK SEG3;
CLK_SEG2_delay: DELAY CLK SEG2;
CLK_SEG1_delay: DELAY CLK SEG1;
CLK_G_delay: DELAY CLK G;
CLK_F_delay: DELAY CLK F;
CLK_E_delay: DELAY CLK E;
CLK_D_delay: DELAY CLK D;
CLK_C_delay: DELAY CLK C;
CLK_B_delay: DELAY CLK B;
CLK_A_delay: DELAY CLK A;
KEY_E_delay: DELAY KEY E;
KEY_E_delay: DELAY KEY E;
KEY_E_delay: DELAY KEY E;
KEY_E_delay: DELAY KEY E;
CLK_SEG8_delay: DELAY CLK SEG8;
CLK_SEG7_delay: DELAY CLK SEG7;
CLK_SEG2_delay: DELAY CLK SEG2;
CLK_G_delay: DELAY CLK G;
CLK_F_delay: DELAY CLK F;
CLK_E_delay: DELAY CLK E;
CLK_D_delay: DELAY CLK D;
CLK_C_delay: DELAY CLK C;
CLK_B_delay: DELAY CLK B;
CLK_A_delay: DELAY CLK A;
KEY_E_delay: DELAY KEY E;
KEY_E_delay: DELAY KEY E;
KEY_E_delay: DELAY KEY E;
KEY_E_delay: DELAY KEY E;
CLK_SEG8_delay: DELAY CLK SEG8;
CLK_SEG7_delay: DELAY CLK SEG7;
CLK_SEG6_delay: DELAY CLK SEG6;
CLK_SEG5_delay: DELAY CLK SEG5;
CLK_SEG4_delay: DELAY CLK SEG4;
CLK_SEG3_delay: DELAY CLK SEG3;
CLK_SEG2_delay: DELAY CLK SEG2;
CLK_SEG1_delay: DELAY CLK SEG1;
CLK_G_delay: DELAY CLK G;
CLK_F_delay: DELAY CLK F;
CLK_E_delay: DELAY CLK E;
CLK_D_delay: DELAY CLK D;
CLK_C_delay: DELAY CLK C;
CLK_B_delay: DELAY CLK B;
CLK_A_delay: DELAY CLK A;
KEY_E_delay: DELAY KEY E;

/* timing check arc definitions */

ENDMODEL