fifo_vhd.vhd

vhdl编写的fifo程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fifo_vhd is
	port(clk,reset,wr,rd : in std_logic;
		  din : in std_logic_vector(3 downto 0);
		  dout : out std_logic_vector(3 downto 0);
		  wpout,rpout : out std_logic_vector(2 downto 0);
		  full,empty : out std_logic);
end fifo_vhd;

architecture behav of fifo_vhd is

type memory is array(0 to 7) of std_logic_vector(3 downto 0);
signal ram : memory;
signal wp : integer range 0 to 7;
signal rp : integer range 0 to 7;
signal in_full,in_empty : std_logic;
signal count : integer range 0 to 10;

begin
	full <= in_full;
	empty <= in_empty;
	dout <= ram(rp);
	wpout <= conv_std_logic_vector(wp,3);
	rpout <= conv_std_logic_vector(rp,3);

	f1:process(clk)
	variable ramd : memory;
		begin
			if(clk'event and clk ='1') then
				if(wr ='0' and in_full ='0') then
					ramd(wp) := din;
				end if;
			ram <= ramd;
			end if;
		end process f1;

	f2:process(clk,reset)
		begin
			if(reset = '1') then
				rp <= 7;
			elsif(clk'event and clk ='1') then	
				if(rd ='0' and in_empty ='0') then
					if(rp = 7) then
						rp <= 0;
					else
						rp <= rp + 1;
					end if;
				end if;
			end if;
		end process f2;
	
	f3:process(clk,reset)
		begin
			if(reset ='1') then
				wp <=0;
			elsif(clk'event and clk ='1') then
				if(wr ='0' and in_full ='0') then
					if(wp = 7) then
						wp <= 0;
					else
						wp <= wp + 1;
					end if;
				end if;
			end if;
		end process f3;

	f4:process(clk,reset)
		begin
			if(reset = '1') then
				in_empty <= '1';
			elsif(clk'event and clk ='1') then
				if(((rp = wp - 2) or (rp = 7 and wp = 1) or(rp = 6 and wp = 0)) and (rd = '0' and wr = '1') )then
					in_empty <= '1';
				else
					in_empty <= '0';
				end if;
			end if;
		end process f4;
					
	f5:process(clk,reset)
		begin
			if(reset = '1') then
				in_full <= '0';
			elsif(clk'event and clk ='1') then
				if(rp = wp and wr ='0' and rd ='1')then
					in_full <= '1';
				else
					in_full <= '0';
				end if;
			end if;
		end process f5;
	
end behav;