conkeep.rpt

来自「电子抢答器 系统复位后进行抢答．超前抢答显示犯规信号」· RPT 代码 · 共 456 行 · 第 1/2 页

        | | | | | | | | | +----- LC24 ~363~1
        | | | | | | | | | | +--- LC25 ~369~1
        | | | | | | | | | | | +- LC29 ~414~1~2
        | | | | | | | | | | | | 
        | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC22 -> * - - - - - - * * - - - | - * | <-- decodeout0
LC21 -> - * - - - - - * * - - * | - * | <-- decodeout1
LC20 -> - - * - - - - * * - - - | - * | <-- decodeout2
LC19 -> - - - * - - - * * - - - | - * | <-- decodeout3
LC18 -> - - - - * - - * * - - - | - * | <-- decodeout4
LC17 -> - - - - - * - * * - - - | - * | <-- decodeout5
LC23 -> * * * * * * - - * * - - | - * | <-- ~360~1
LC24 -> - - - - - - * - - - * - | - * | <-- ~363~1
LC25 -> - - - - - - - * * * - - | - * | <-- ~369~1
LC29 -> - * - - - - - - - - - - | - * | <-- ~414~1~2

Pin
4    -> * * * * * * * - * - * * | - * | <-- reset
5    -> - * * * * - - - * * - * | - * | <-- s0
6    -> * * - * * - - - * * - * | - * | <-- s1
7    -> * * * * * - - - * * - * | - * | <-- s2
8    -> * * * * * - - - * * - * | - * | <-- s3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                 e:\0110200330\fourcon\conkeep.rpt
conkeep

** EQUATIONS **

reset    : INPUT;
s0       : INPUT;
s1       : INPUT;
s2       : INPUT;
s3       : INPUT;

-- Node name is 'decodeout0' = '~423~1' 
-- Equation name is 'decodeout0', location is LC022, type is output.
 decodeout0 = LCELL( _EQ001 $ !reset);
  _EQ001 =  _LC023 & !reset & !s1 & !s2 & !s3
         # !decodeout0 & !_LC023 & !reset
         # !decodeout0 & !reset & !s1 & !s2 & !s3;

-- Node name is 'decodeout1' = '~414~1' 
-- Equation name is 'decodeout1', location is LC021, type is output.
 decodeout1 = LCELL( _EQ002 $  VCC);
  _EQ002 =  _LC023 & !reset &  s0 & !s1 & !s2 & !s3
         #  _LC023 & !reset & !s0 &  s1 & !s2 & !s3
         #  _LC023 & !reset & !s0 & !s1 &  s2 & !s3
         # !decodeout1 & !_LC023 & !reset
         #  _LC029;

-- Node name is 'decodeout2' = '~405~1' 
-- Equation name is 'decodeout2', location is LC020, type is output.
 decodeout2 = LCELL( _EQ003 $  reset);
  _EQ003 =  _LC023 & !reset & !s0 & !s2 & !s3
         #  decodeout2 & !_LC023 & !reset
         #  decodeout2 & !reset & !s0 & !s2 & !s3;

-- Node name is 'decodeout3' = '~396~1' 
-- Equation name is 'decodeout3', location is LC019, type is output.
 decodeout3 = LCELL( _EQ004 $  VCC);
  _EQ004 =  _LC023 & !reset &  s0 & !s1 & !s2 & !s3
         #  _LC023 & !reset & !s0 & !s1 & !s2 &  s3
         # !decodeout3 & !_LC023 & !reset
         # !decodeout3 & !reset &  s0 & !s1 & !s2 & !s3
         # !decodeout3 & !reset & !s0 & !s1 & !s2 &  s3;

-- Node name is 'decodeout4' = '~387~1' 
-- Equation name is 'decodeout4', location is LC018, type is output.
 decodeout4 = LCELL( _EQ005 $  VCC);
  _EQ005 =  _LC023 & !reset & !s0 &  s1 & !s2 & !s3
         # !decodeout4 & !_LC023 & !reset
         # !decodeout4 & !reset & !s0 &  s1 & !s2 & !s3;

-- Node name is 'decodeout5' = '~378~1' 
-- Equation name is 'decodeout5', location is LC017, type is output.
 decodeout5 = LCELL( _EQ006 $  VCC);
  _EQ006 = !decodeout5 & !_LC023 & !reset;

-- Node name is 'decodeout6' 
-- Equation name is 'decodeout6', location is LC027, type is output.
 decodeout6 = LCELL( _EQ007 $  reset);
  _EQ007 =  _LC024 & !reset;

-- Node name is 'f' 
-- Equation name is 'f', location is LC026, type is output.
 f       = LCELL( _EQ008 $  VCC);
  _EQ008 = !decodeout0 &  decodeout1 &  decodeout2 &  decodeout3 & 
              decodeout4 &  decodeout5 &  _LC025;

-- Node name is '~360~1' 
-- Equation name is '~360~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ009 $  GND);
  _EQ009 = !decodeout0 &  decodeout1 &  decodeout2 &  decodeout3 & 
              decodeout4 &  decodeout5 & !_LC023 &  _LC025
         # !decodeout0 &  _LC023 &  _LC025 & !s0 & !s1 & !s2 & !s3
         # !decodeout0 &  _LC025 &  reset
         # !decodeout0 &  decodeout1 &  decodeout2 &  decodeout3 & 
              decodeout4 &  decodeout5 &  _LC025 & !s0 & !s1 & !s2 & !s3;

-- Node name is '~363~1' 
-- Equation name is '~363~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ010 $  VCC);
  _EQ010 =  _LC023 &  s0 & !s1 & !s2 & !s3
         #  _LC023 & !s0 & !s1 & !s2 &  s3
         # !_LC023 & !_LC025;

-- Node name is '~369~1' 
-- Equation name is '~369~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ011 $  VCC);
  _EQ011 = !_LC024 & !reset;

-- Node name is '~414~1~2' 
-- Equation name is '~414~1~2', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ012 $  GND);
  _EQ012 = !decodeout1 & !reset &  s0 & !s1 & !s2 & !s3
         # !decodeout1 & !reset & !s0 &  s1 & !s2 & !s3
         # !decodeout1 & !reset & !s0 & !s1 &  s2 & !s3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                          e:\0110200330\fourcon\conkeep.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,195K