conkeep.rpt
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RPT
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Project Information e:\0110200330\fourcon\conkeep.rpt
MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 11/29/2004 23:06:44
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
CONKEEP
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
conkeep EPM7032LC44-6 5 8 0 12 0 37 %
User Pins: 5 8 0
Device-Specific Information: e:\0110200330\fourcon\conkeep.rpt
conkeep
***** Logic for device 'conkeep' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
d d
e e
c c
o o
d d
r e e
e o o
s V G G G G G u u
s s e C N N N N N t t
1 0 t C D D D D D 5 4
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
s2 | 7 39 | decodeout3
s3 | 8 38 | decodeout2
RESERVED | 9 37 | decodeout1
GND | 10 36 | decodeout0
RESERVED | 11 35 | VCC
RESERVED | 12 EPM7032LC44-6 34 | RESERVED
RESERVED | 13 33 | RESERVED
RESERVED | 14 32 | RESERVED
VCC | 15 31 | f
RESERVED | 16 30 | GND
RESERVED | 17 29 | decodeout6
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\0110200330\fourcon\conkeep.rpt
conkeep
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 5/16( 31%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 12/16( 75%) 8/16( 50%) 2/16( 12%) 15/36( 41%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 13/32 ( 40%)
Total logic cells used: 12/32 ( 37%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 12/32 ( 37%)
Total shareable expanders not available (n/a): 2/32 ( 6%)
Average fan-in: 6.08
Total fan-in: 73
Total input pins required: 5
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 12
Total flipflops required: 0
Total product terms required: 36
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 10/ 32 ( 31%)
Device-Specific Information: e:\0110200330\fourcon\conkeep.rpt
conkeep
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 7 3 reset
5 (2) (A) INPUT 0 0 0 0 0 4 3 s0
6 (3) (A) INPUT 0 0 0 0 0 4 3 s1
7 (4) (A) INPUT 0 0 0 0 0 5 3 s2
8 (5) (A) INPUT 0 0 0 0 0 5 3 s3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\0110200330\fourcon\conkeep.rpt
conkeep
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
36 22 B OUTPUT s t 0 0 0 4 2 2 1 decodeout0
37 21 B OUTPUT s t 1 0 1 5 3 2 2 decodeout1
38 20 B OUTPUT s t 0 0 0 4 2 2 1 decodeout2
39 19 B OUTPUT s t 1 0 1 5 2 2 1 decodeout3
40 18 B OUTPUT s t 0 0 0 5 2 2 1 decodeout4
41 17 B OUTPUT s t 0 0 0 1 2 2 1 decodeout5
29 27 B OUTPUT t 0 0 0 1 1 0 0 decodeout6
31 26 B OUTPUT t 0 0 0 0 7 0 0 f
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\0110200330\fourcon\conkeep.rpt
conkeep
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(34) 23 B LCELL s t 0 0 0 5 8 6 2 ~360~1
(33) 24 B SOFT s t 0 0 0 4 2 1 1 ~363~1
(32) 25 B LCELL s t 0 0 0 1 1 1 2 ~369~1
(27) 29 B LCELL s t 0 0 0 5 1 1 0 ~414~1~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\0110200330\fourcon\conkeep.rpt
conkeep
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------- LC22 decodeout0
| +--------------------- LC21 decodeout1
| | +------------------- LC20 decodeout2
| | | +----------------- LC19 decodeout3
| | | | +--------------- LC18 decodeout4
| | | | | +------------- LC17 decodeout5
| | | | | | +----------- LC27 decodeout6
| | | | | | | +--------- LC26 f
| | | | | | | | +------- LC23 ~360~1
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