console.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity console is port
	(	
	 	k1,k2,k3,k4,nen,prohibit	:in std_logic;
	 	decodeout				:out	std_logic_vector(3 downto 0);
		buzzeren				:out  std_logic
	);
end console;

architecture truthtable of console is
begin
	process(k1,k2,k3,k4)
	begin
		buzzeren<='0';
		if(prohibit='0')then
			if(nen='0')then
				if(k1='0' and k2='0' and k3='0' and k4='0')then
					decodeout<="0000";		
				elsif(k1='1' and k2='0' and k3='0' and k4='0')then
					decodeout<="0001";
					buzzeren<='1';
				elsif(k1='0' and k2='1' and k3='0' and k4='0')then
					decodeout<="0010";
					buzzeren<='1';
				elsif(k1='0' and k2='0' and k3='1' and k4='0')then
					decodeout<="0100";
					buzzeren<='1';
				elsif(k1='0' and k2='0' and k3='0' and k4='1')then
					decodeout<="1000";
					buzzeren<='1';
				else
					decodeout<="1111";
					buzzeren<='1';
				end if;
			elsif(k1='0' and k2='0' and k3='0' and k4='0')then
				decodeout<="0000";
			end if;
		end if;					
	end process;
end truthtable;