constate.vhd

来自「电子抢答器 系统复位后进行抢答．超前抢答显示犯规信号」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity constate is port
	(	
	 	start,ci,di		:in std_logic;
	 	decodeout	:out	std_logic_vector(2 downto 0)
	);
end constate;

architecture truthtable of constate is
begin
	process(start,ci,di)
	begin
		if(start='0')then
			if(ci='1')then
				decodeout<="111";
			else
				decodeout<="000";
			end if;
		elsif(di='0')then
			if(ci='0')then
				decodeout<="001";
			else
				decodeout<="010";
			end if;
		elsif(di='1')then
			decodeout<="100";
		end if;		
	end process;
end truthtable;