dcntm20.rpt

电子抢答器 系统复位后进行抢答．超前抢答显示犯规信号

+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                 e:\0110200330\fourcon\dcntm20.rpt
dcntm20

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC26 co
        | +------------------- LC25 |LPM_ADD_SUB:106|addcore:adder|addcore:adder0|gcp2
        | | +----------------- LC27 |LPM_ADD_SUB:131|addcore:adder|addcore:adder0|gcp2
        | | | +--------------- LC18 qh0
        | | | | +------------- LC19 qh1
        | | | | | +----------- LC17 qh2
        | | | | | | +--------- LC20 qh3
        | | | | | | | +------- LC24 ql0
        | | | | | | | | +----- LC23 ql1
        | | | | | | | | | +--- LC22 ql2
        | | | | | | | | | | +- LC21 ql3
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC25 -> - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:106|addcore:adder|addcore:adder0|gcp2
LC27 -> - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:131|addcore:adder|addcore:adder0|gcp2
LC18 -> * - - * * * * * - - * | - * | <-- qh0
LC19 -> * * - * * * * * - - * | - * | <-- qh1
LC17 -> * * - * * * * * - - * | - * | <-- qh2
LC20 -> * - - * * * * * - - * | - * | <-- qh3
LC24 -> * - - * * * * * * * * | - * | <-- ql0
LC23 -> * - * * * * * * * * * | - * | <-- ql1
LC22 -> * - * * * * * * * * * | - * | <-- ql2
LC21 -> * - - * * * * * * * * | - * | <-- ql3

Pin
43   -> - - - - - - - - - - - | - - | <-- clk
5    -> - - - * * * * * * * * | - * | <-- reset
4    -> * - - * * * * * * * * | - * | <-- start
6    -> - - - * * * * * * * * | - * | <-- stop


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                 e:\0110200330\fourcon\dcntm20.rpt
dcntm20

** EQUATIONS **

clk      : INPUT;
reset    : INPUT;
start    : INPUT;
stop     : INPUT;

-- Node name is 'co' 
-- Equation name is 'co', location is LC026, type is output.
 co      = LCELL( _EQ001 $  GND);
  _EQ001 = !qh0 & !qh1 & !qh2 & !qh3 & !ql0 & !ql1 & !ql2 & !ql3 &  start;

-- Node name is 'qh0' = ':12' 
-- Equation name is 'qh0', type is output 
 qh0     = TFFE( _EQ002, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ002 = !qh0 &  qh3 & !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop
         # !qh0 &  qh2 & !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop
         # !qh0 &  qh1 & !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop
         #  qh0 & !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop;

-- Node name is 'qh1' = ':10' 
-- Equation name is 'qh1', type is output 
 qh1     = TFFE( _EQ003, GLOBAL( clk),  VCC, !reset,  VCC);
  _EQ003 = !qh0 & !qh1 &  qh3 & !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop
         # !qh0 & !qh1 &  qh2 & !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop
         # !qh0 &  qh1 & !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop;

-- Node name is 'qh2' = ':8' 
-- Equation name is 'qh2', type is output 
 qh2     = TFFE( _EQ004, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ004 = !qh0 & !qh1 & !qh2 &  qh3 & !ql0 & !ql1 & !ql2 & !ql3 &  start & 
             !stop
         # !qh0 & !qh1 &  qh2 & !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop;

-- Node name is 'qh3' = ':6' 
-- Equation name is 'qh3', type is output 
 qh3     = TFFE( _EQ005, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ005 = !_LC025 & !qh0 &  qh2 & !qh3 & !ql0 & !ql1 & !ql2 & !ql3 &  start & 
             !stop
         # !_LC025 & !qh0 &  qh1 & !qh3 & !ql0 & !ql1 & !ql2 & !ql3 &  start & 
             !stop
         # !_LC025 & !qh0 &  qh3 & !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop;

-- Node name is 'ql0' = ':20' 
-- Equation name is 'ql0', type is output 
 ql0     = TFFE(!_EQ006, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ006 = !qh0 & !qh1 & !qh2 & !qh3 & !ql0 & !ql1 & !ql2 & !ql3
         #  stop
         # !start;

-- Node name is 'ql1' = ':18' 
-- Equation name is 'ql1', type is output 
 ql1     = TFFE( _EQ007, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ007 = !ql0 & !ql1 &  ql3 &  start & !stop
         # !ql0 & !ql1 &  ql2 &  start & !stop
         # !ql0 &  ql1 &  start & !stop;

-- Node name is 'ql2' = ':16' 
-- Equation name is 'ql2', type is output 
 ql2     = TFFE( _EQ008, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ008 = !ql0 & !ql1 & !ql2 &  ql3 &  start & !stop
         # !ql0 & !ql1 &  ql2 &  start & !stop;

-- Node name is 'ql3' = ':14' 
-- Equation name is 'ql3', type is output 
 ql3     = TFFE( _EQ009, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ009 = !ql0 & !ql1 & !ql2 & !ql3 &  start & !stop &  _X001
         # !_LC027 & !ql0 & !ql3 &  start & !stop &  _X002
         # !_LC027 & !ql0 &  ql3 &  start & !stop;
  _X001  = EXP(!qh0 & !qh1 & !qh2 & !qh3);
  _X002  = EXP(!ql1 & !ql2);

-- Node name is '|LPM_ADD_SUB:106|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( _EQ010 $  qh2);
  _EQ010 =  qh1 & !qh2;

-- Node name is '|LPM_ADD_SUB:131|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( _EQ011 $  ql2);
  _EQ011 =  ql1 & !ql2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                          e:\0110200330\fourcon\dcntm20.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,076K