fourcon.vhd

电子抢答器 系统复位后进行抢答．超前抢答显示犯规信号

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fourcon is port
	(
	 k1,k2,k3,k4,clk1,clk2,reset,start		:in std_logic;
	 buzzerout			:out 	std_logic;
	 out1				:out	std_logic_vector(2 downto 0);
	 dcout			:out	std_logic_vector(6 downto 0);
	 out2				:buffer std_logic_vector(2 downto 0)
);	 
end fourcon;

architecture arch of fourcon is

component console is port
	(	
	 	k1,k2,k3,k4,nen,prohibit	:in std_logic;
	 	decodeout				:out	std_logic_vector(3 downto 0);
		buzzeren				:out  std_logic
	);
end component;

component conkeep is port
	(	
	 	reset		:in std_logic;
	 	s			:in std_logic_vector(3 downto 0);
	 	decodeout	:buffer	std_logic_vector(6 downto 0);
		f			:buffer std_logic
	);
end component;

component constate is port
	(	
	 	start,ci,di		:in std_logic;
	 	decodeout	:out	std_logic_vector(2 downto 0)
	);
end component;

component dcntm20 is port
	(	start,stop		:in std_logic;
	 	reset		:in std_logic;
	 	clk			:in std_logic;
	 	co			:buffer std_logic;
	 	qh			:buffer std_logic_vector(3 downto 0);
	 	ql			:buffer std_logic_vector(3 downto 0)
	);
end component;

component decode47 is port
	(adr		:in std_logic_vector(3 downto 0);
	 decodeout	:out std_logic_vector(6 downto 0)
	);
end component;

component v3mux1 is port
	(
	 clk				:in std_logic;
	 decodein1,decodein2,decodein3	:in std_logic_vector(6 downto 0);
	 dataout		:buffer std_logic_vector(2 downto 0);
	 decodeout	:out std_logic_vector(6 downto 0)
	);
end component;

component buzzer is port
	(	
	 	clk,en		:in std_logic;
	 	buzzerout		:out std_logic
	);
end component;

signal dc1,dc2,dc3	:std_logic_vector(6 downto 0);
signal a,qh,ql: std_logic_vector(3 downto 0);
signal b,c,d: std_logic;

begin
	u1:console port map(k1,k2,k3,k4,c,d,a,b);
	u2:conkeep port map(reset,a,dc3,c);
	u3:constate port map(start,c,d,out1);
	u4:dcntm20 port map(start,c,reset,clk1,d,qh,ql);
	u5:decode47 port map(qh,dc1);
	u6:decode47 port map(ql,dc2);
	u7:buzzer port map(clk2,b,buzzerout);
	u8:v3mux1 port map(clk2,dc1,dc2,dc3,out2,dcout);
end arch;