dcntm20.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dcntm20 is 
	port
	(	start,stop		:in std_logic;
	 	reset		:in std_logic;
	 	clk			:in std_logic;
	 	co			:buffer std_logic;
	 	qh			:buffer std_logic_vector(3 downto 0);
	 	ql			:buffer std_logic_vector(3 downto 0)
	);
end dcntm20;

architecture truthtable of dcntm20 is
begin
	co<='1'when(qh="0000" and ql="0000" and start='1')else'0';
	process(clk,reset)
		begin
				if(reset='1')then
						qh<="0010";
						ql<="0000";
					elsif(clk'event and clk='1')then
						if(start='1' and stop='0' and co='0')then
							if(ql="0000") then
								ql<="1001";
								qh<=qh-1;
							else
								ql<=ql-1;
							end if;
						end if;
				end if;							
	end process;
end truthtable;