📄 fourcon.rpt
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-- Node name is '|decode47:u5|:368'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ054);
_EQ054 = _LC4_C12
# !_LC5_C12
# _LC6_C12 & _LC8_C12
# !_LC6_C12 & !_LC8_C12;
-- Node name is '|decode47:u5|:430'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ055);
_EQ055 = _LC4_C12
# _LC6_C12 & !_LC8_C12
# !_LC5_C12 & !_LC8_C12
# !_LC5_C12 & _LC6_C12
# _LC5_C12 & !_LC6_C12 & _LC8_C12;
-- Node name is '|decode47:u5|:460'
-- Equation name is '_LC8_C2', type is buried
_LC8_C2 = LCELL( _EQ056);
_EQ056 = !_LC4_C12 & _LC6_C12 & !_LC8_C12
# _LC4_C12 & !_LC5_C12 & !_LC6_C12 & !_LC8_C12;
-- Node name is '|decode47:u5|:490'
-- Equation name is '_LC8_C1', type is buried
_LC8_C1 = LCELL( _EQ057);
_EQ057 = !_LC1_C2 & _LC4_C1 & !_LC6_C1;
-- Node name is '|decode47:u6|:299'
-- Equation name is '_LC1_C3', type is buried
!_LC1_C3 = _LC1_C3~NOT;
_LC1_C3~NOT = LCELL( _EQ058);
_EQ058 = _LC5_C6
# _LC4_C6
# !_LC2_C12
# !_LC3_C12;
-- Node name is '|decode47:u6|:311'
-- Equation name is '_LC3_C3', type is buried
!_LC3_C3 = _LC3_C3~NOT;
_LC3_C3~NOT = LCELL( _EQ059);
_EQ059 = _LC5_C6
# _LC4_C6
# !_LC3_C12
# _LC2_C12;
-- Node name is '|decode47:u6|:340'
-- Equation name is '_LC6_C6', type is buried
_LC6_C6 = LCELL( _EQ060);
_EQ060 = _LC5_C6
# _LC3_C12
# _LC2_C12 & _LC4_C6
# !_LC2_C12 & !_LC4_C6;
-- Node name is '|decode47:u6|:368'
-- Equation name is '_LC7_C3', type is buried
_LC7_C3 = LCELL( _EQ061);
_EQ061 = _LC5_C6
# !_LC4_C6
# !_LC2_C12 & !_LC3_C12
# _LC2_C12 & _LC3_C12;
-- Node name is '|decode47:u6|:430'
-- Equation name is '_LC8_C6', type is buried
_LC8_C6 = LCELL( _EQ062);
_EQ062 = _LC5_C6
# !_LC2_C12 & _LC3_C12
# !_LC2_C12 & !_LC4_C6
# _LC3_C12 & !_LC4_C6
# _LC2_C12 & !_LC3_C12 & _LC4_C6;
-- Node name is '|decode47:u6|:460'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = LCELL( _EQ063);
_EQ063 = !_LC2_C12 & _LC3_C12 & !_LC5_C6
# !_LC2_C12 & !_LC3_C12 & !_LC4_C6 & _LC5_C6;
-- Node name is '|decode47:u6|:490'
-- Equation name is '_LC2_C3', type is buried
_LC2_C3 = LCELL( _EQ064);
_EQ064 = !_LC1_C3 & !_LC3_C3 & _LC3_C6;
-- Node name is '|v3mux1:u8|:23'
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = DFFE( _EQ065, GLOBAL( clk2), VCC, VCC, VCC);
_EQ065 = !_LC1_C20 & !_LC4_C20;
-- Node name is '|v3mux1:u8|:25'
-- Equation name is '_LC3_C1', type is buried
_LC3_C1 = DFFE( _LC1_C20, GLOBAL( clk2), VCC, VCC, VCC);
-- Node name is '|v3mux1:u8|:27'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _LC4_C20, GLOBAL( clk2), VCC, VCC, VCC);
-- Node name is '|v3mux1:u8|:29'
-- Equation name is '_LC4_C4', type is buried
_LC4_C4 = DFFE( _EQ066, GLOBAL( clk2), VCC, VCC, VCC);
_EQ066 = !_LC4_C20 & _LC8_C4
# _LC2_A1 & _LC4_C20
# _LC4_C20 & _LC6_A1;
-- Node name is '|v3mux1:u8|:31'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = DFFE( _EQ067, GLOBAL( clk2), VCC, VCC, VCC);
_EQ067 = _LC3_A1 & _LC4_C20
# !_LC4_C20 & _LC8_C3;
-- Node name is '|v3mux1:u8|:33'
-- Equation name is '_LC4_C3', type is buried
_LC4_C3 = DFFE( _EQ068, GLOBAL( clk2), VCC, VCC, VCC);
_EQ068 = !_LC4_C20 & _LC6_C3
# !_LC1_C2 & _LC4_C20;
-- Node name is '|v3mux1:u8|:35'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = DFFE( _EQ069, GLOBAL( clk2), VCC, VCC, VCC);
_EQ069 = !_LC4_C20 & _LC5_C4
# _LC4_A1 & _LC4_C20
# _LC4_C20 & _LC6_A1;
-- Node name is '|v3mux1:u8|:37'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = DFFE( _EQ070, GLOBAL( clk2), VCC, VCC, VCC);
_EQ070 = !_LC4_C20 & _LC7_C2
# _LC4_C20 & _LC8_C2
# _LC4_C20 & _LC6_A1;
-- Node name is '|v3mux1:u8|:39'
-- Equation name is '_LC7_C1', type is buried
_LC7_C1 = DFFE( _EQ071, GLOBAL( clk2), VCC, VCC, VCC);
_EQ071 = !_LC4_C20 & _LC5_C1
# _LC4_C20 & _LC8_C1
# _LC4_C20 & _LC6_A1;
-- Node name is '|v3mux1:u8|:41'
-- Equation name is '_LC1_C1', type is buried
_LC1_C1 = DFFE( _EQ072, GLOBAL( clk2), VCC, VCC, VCC);
_EQ072 = _LC2_C1 & !_LC4_C20
# _LC4_C1 & _LC4_C20 & !_LC6_A1;
-- Node name is '|v3mux1:u8|:98'
-- Equation name is '_LC4_C20', type is buried
_LC4_C20 = LCELL( _EQ073);
_EQ073 = !_LC1_A1 & !_LC3_C1 & _LC7_C11;
-- Node name is '|v3mux1:u8|:105'
-- Equation name is '_LC1_C20', type is buried
_LC1_C20 = LCELL( _EQ074);
_EQ074 = _LC1_A1 & !_LC3_C1 & !_LC7_C11;
-- Node name is '|v3mux1:u8|:306'
-- Equation name is '_LC8_C4', type is buried
_LC8_C4 = LCELL( _EQ075);
_EQ075 = !_LC1_C20 & _LC7_C4
# _LC1_C20 & _LC6_C6
# _LC1_C6 & _LC1_C20;
-- Node name is '|v3mux1:u8|:318'
-- Equation name is '_LC8_C3', type is buried
_LC8_C3 = LCELL( _EQ076);
_EQ076 = _LC1_C8 & !_LC1_C20
# _LC1_C20 & _LC7_C3;
-- Node name is '|v3mux1:u8|:330'
-- Equation name is '_LC6_C3', type is buried
_LC6_C3 = LCELL( _EQ077);
_EQ077 = !_LC1_C20 & _LC4_C2
# _LC1_C20 & !_LC3_C3;
-- Node name is '|v3mux1:u8|:342'
-- Equation name is '_LC5_C4', type is buried
_LC5_C4 = LCELL( _EQ078);
_EQ078 = !_LC1_C20 & _LC3_C4
# _LC1_C20 & _LC8_C6
# _LC1_C6 & _LC1_C20;
-- Node name is '|v3mux1:u8|:354'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = LCELL( _EQ079);
_EQ079 = !_LC1_C20 & _LC2_C2
# _LC1_C20 & _LC2_C6
# _LC1_C6 & _LC1_C20;
-- Node name is '|v3mux1:u8|:366'
-- Equation name is '_LC5_C1', type is buried
_LC5_C1 = LCELL( _EQ080);
_EQ080 = !_LC1_C20 & _LC3_C20
# _LC1_C20 & _LC2_C3
# _LC1_C6 & _LC1_C20;
-- Node name is '|v3mux1:u8|:378'
-- Equation name is '_LC2_C1', type is buried
_LC2_C1 = LCELL( _EQ081);
_EQ081 = !_LC1_C20 & _LC2_C20
# !_LC1_C6 & _LC1_C20 & _LC3_C6;
-- Node name is '|v3mux1:u8|~379~1'
-- Equation name is '_LC3_C6', type is buried
-- synthesized logic cell
_LC3_C6 = LCELL( _EQ082);
_EQ082 = _LC5_C6
# !_LC2_C12
# _LC3_C12 & !_LC4_C6
# !_LC3_C12 & _LC4_C6;
-- Node name is '|v3mux1:u8|~382~1'
-- Equation name is '_LC4_C1', type is buried
-- synthesized logic cell
_LC4_C1 = LCELL( _EQ083);
_EQ083 = _LC4_C12
# !_LC8_C12
# !_LC5_C12 & _LC6_C12
# _LC5_C12 & !_LC6_C12;
Project Information d:\maxplus2\0110200330\fourcon.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,392K
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