📄 fourcon.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\maxplus2\0110200330\fourcon.rpt
fourcon
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 15 OR2 1 2 1 0 |buzzer:u7|:20
- 3 - C 02 OR2 ! 0 4 0 1 |conkeep:u2|:209
- 6 - C 02 AND2 0 3 0 1 |conkeep:u2|:308
- 8 - C 20 OR2 0 4 0 1 |conkeep:u2|:326
- 2 - C 04 OR2 s 0 4 0 2 |conkeep:u2|~369~1
- 7 - C 04 OR2 1 2 0 2 |conkeep:u2|:369
- 1 - C 08 OR2 1 0 0 2 |conkeep:u2|:378
- 4 - C 02 OR2 1 2 0 2 |conkeep:u2|:387
- 3 - C 04 OR2 1 2 0 2 |conkeep:u2|:396
- 2 - C 02 OR2 1 2 0 2 |conkeep:u2|:405
- 3 - C 20 OR2 1 2 0 2 |conkeep:u2|:414
- 6 - C 20 OR2 s 0 3 0 1 |conkeep:u2|~421~1
- 2 - C 20 OR2 1 2 0 2 |conkeep:u2|:423
- 1 - C 04 AND2 s ! 0 4 0 1 |conkeep:u2|~441~1
- 6 - C 04 AND2 0 4 0 15 |conkeep:u2|:441
- 5 - C 21 OR2 ! 4 0 0 6 |console:u1|:142
- 4 - C 21 AND2 4 0 0 3 |console:u1|:152
- 1 - C 21 OR2 ! 4 0 0 3 |console:u1|:162
- 2 - C 21 OR2 ! 4 0 0 3 |console:u1|:172
- 3 - C 21 OR2 ! 4 0 0 3 |console:u1|:182
- 2 - C 15 OR2 0 3 0 1 |console:u1|:322
- 7 - C 15 OR2 0 4 0 1 |console:u1|:343
- 5 - C 18 OR2 s 0 4 0 1 |console:u1|~386~1
- 4 - C 18 OR2 s 0 4 0 1 |console:u1|~395~1
- 8 - C 15 AND2 s 0 3 0 2 |console:u1|~396~1
- 5 - C 15 OR2 s 0 4 0 1 |console:u1|~404~1
- 2 - C 18 AND2 s 0 2 0 3 |console:u1|~431~1
- 7 - C 18 OR2 0 3 0 6 |console:u1|:436
- 6 - C 18 OR2 0 3 0 6 |console:u1|:442
- 4 - C 15 OR2 0 3 0 5 |console:u1|:448
- 6 - C 15 OR2 s 0 4 0 1 |console:u1|~454~1
- 3 - C 15 OR2 0 4 0 5 |console:u1|:454
- 7 - C 20 OR2 1 3 1 0 |constate:u3|:145
- 5 - C 20 OR2 1 3 1 0 |constate:u3|:157
- 3 - C 18 OR2 1 2 1 0 |constate:u3|:169
- 7 - C 12 AND2 ! 0 2 0 1 |dcntm20:u4|LPM_ADD_SUB:106|addcore:adder|pcarry1
- 1 - C 12 OR2 0 3 0 2 |dcntm20:u4|LPM_ADD_SUB:106|addcore:adder|pcarry2
- 7 - C 06 OR2 0 2 0 3 |dcntm20:u4|LPM_ADD_SUB:131|addcore:adder|pcarry1
- 4 - C 12 DFFE + 1 3 0 8 |dcntm20:u4|:6
- 5 - C 12 DFFE + 1 3 0 8 |dcntm20:u4|:8
- 6 - C 12 DFFE + ! 1 3 0 9 |dcntm20:u4|:10
- 8 - C 12 DFFE + 1 2 0 10 |dcntm20:u4|:12
- 5 - C 06 DFFE + 1 3 0 8 |dcntm20:u4|:14
- 4 - C 06 DFFE + 1 3 0 9 |dcntm20:u4|:16
- 3 - C 12 DFFE + 1 3 0 8 |dcntm20:u4|:18
- 2 - C 12 DFFE + 1 1 0 9 |dcntm20:u4|:20
- 8 - C 18 AND2 1 1 0 8 |dcntm20:u4|:75
- 1 - C 06 OR2 ! 0 3 0 14 |dcntm20:u4|:85
- 1 - C 18 OR2 ! 1 2 0 6 |dcntm20:u4|:304
- 6 - C 01 OR2 ! 0 4 0 1 |decode47:u5|:299
- 1 - C 02 OR2 ! 0 4 0 2 |decode47:u5|:311
- 6 - A 01 OR2 ! 0 2 0 8 |decode47:u5|:335
- 2 - A 01 OR2 0 4 0 1 |decode47:u5|:340
- 3 - A 01 OR2 0 4 0 1 |decode47:u5|:368
- 4 - A 01 OR2 0 4 0 1 |decode47:u5|:430
- 8 - C 02 OR2 0 4 0 1 |decode47:u5|:460
- 8 - C 01 AND2 0 3 0 1 |decode47:u5|:490
- 1 - C 03 OR2 ! 0 4 0 1 |decode47:u6|:299
- 3 - C 03 OR2 ! 0 4 0 2 |decode47:u6|:311
- 6 - C 06 OR2 0 4 0 1 |decode47:u6|:340
- 7 - C 03 OR2 0 4 0 1 |decode47:u6|:368
- 8 - C 06 OR2 0 4 0 1 |decode47:u6|:430
- 2 - C 06 OR2 0 4 0 1 |decode47:u6|:460
- 2 - C 03 AND2 0 3 0 1 |decode47:u6|:490
- 7 - C 11 DFFE + 0 2 1 2 |v3mux1:u8|:23
- 3 - C 01 DFFE + 0 1 1 2 |v3mux1:u8|:25
- 1 - A 01 DFFE + 0 1 1 2 |v3mux1:u8|:27
- 4 - C 04 DFFE + 0 4 1 0 |v3mux1:u8|:29
- 5 - C 03 DFFE + 0 3 1 0 |v3mux1:u8|:31
- 4 - C 03 DFFE + 0 3 1 0 |v3mux1:u8|:33
- 8 - A 01 DFFE + 0 4 1 0 |v3mux1:u8|:35
- 5 - C 02 DFFE + 0 4 1 0 |v3mux1:u8|:37
- 7 - C 01 DFFE + 0 4 1 0 |v3mux1:u8|:39
- 1 - C 01 DFFE + 0 4 1 0 |v3mux1:u8|:41
- 4 - C 20 AND2 0 3 0 9 |v3mux1:u8|:98
- 1 - C 20 AND2 0 3 0 9 |v3mux1:u8|:105
- 8 - C 04 OR2 0 4 0 1 |v3mux1:u8|:306
- 8 - C 03 OR2 0 3 0 1 |v3mux1:u8|:318
- 6 - C 03 OR2 0 3 0 1 |v3mux1:u8|:330
- 5 - C 04 OR2 0 4 0 1 |v3mux1:u8|:342
- 7 - C 02 OR2 0 4 0 1 |v3mux1:u8|:354
- 5 - C 01 OR2 0 4 0 1 |v3mux1:u8|:366
- 2 - C 01 OR2 0 4 0 1 |v3mux1:u8|:378
- 3 - C 06 OR2 s 0 4 0 2 |v3mux1:u8|~379~1
- 4 - C 01 OR2 s 0 4 0 2 |v3mux1:u8|~382~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\maxplus2\0110200330\fourcon.rpt
fourcon
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 32/ 96( 33%) 13/ 48( 27%) 8/ 48( 16%) 3/16( 18%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 7/24( 29%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 6/24( 25%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\maxplus2\0110200330\fourcon.rpt
fourcon
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk2
INPUT 8 clk1
Device-Specific Information: d:\maxplus2\0110200330\fourcon.rpt
fourcon
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 15 reset
Device-Specific Information: d:\maxplus2\0110200330\fourcon.rpt
fourcon
** EQUATIONS **
clk1 : INPUT;
clk2 : INPUT;
k1 : INPUT;
k2 : INPUT;
k3 : INPUT;
k4 : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is 'buzzerout'
-- Equation name is 'buzzerout', type is output
buzzerout = _LC1_C15;
-- Node name is 'dcout0'
-- Equation name is 'dcout0', type is output
dcout0 = _LC1_C1;
-- Node name is 'dcout1'
-- Equation name is 'dcout1', type is output
dcout1 = _LC7_C1;
-- Node name is 'dcout2'
-- Equation name is 'dcout2', type is output
dcout2 = _LC5_C2;
-- Node name is 'dcout3'
-- Equation name is 'dcout3', type is output
dcout3 = _LC8_A1;
-- Node name is 'dcout4'
-- Equation name is 'dcout4', type is output
dcout4 = _LC4_C3;
-- Node name is 'dcout5'
-- Equation name is 'dcout5', type is output
dcout5 = _LC5_C3;
-- Node name is 'dcout6'
-- Equation name is 'dcout6', type is output
dcout6 = _LC4_C4;
-- Node name is 'out10'
-- Equation name is 'out10', type is output
out10 = _LC3_C18;
-- Node name is 'out11'
-- Equation name is 'out11', type is output
out11 = _LC5_C20;
-- Node name is 'out12'
-- Equation name is 'out12', type is output
out12 = _LC7_C20;
-- Node name is 'out20'
-- Equation name is 'out20', type is output
out20 = _LC1_A1;
-- Node name is 'out21'
-- Equation name is 'out21', type is output
out21 = _LC3_C1;
-- Node name is 'out22'
-- Equation name is 'out22', type is output
out22 = _LC7_C11;
-- Node name is '|buzzer:u7|:20'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = LCELL( _EQ001);
_EQ001 = clk2 & _LC2_C18 & !_LC5_C21
# _LC1_C15 & _LC5_C21
# _LC1_C15 & !_LC2_C18;
-- Node name is '|conkeep:u2|:209'
-- Equation name is '_LC3_C2', type is buried
!_LC3_C2 = _LC3_C2~NOT;
_LC3_C2~NOT = LCELL( _EQ002);
_EQ002 = _LC7_C18
# _LC6_C18
# _LC3_C15
# !_LC4_C15;
-- Node name is '|conkeep:u2|:308'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = LCELL( _EQ003);
_EQ003 = !_LC3_C15 & !_LC6_C18 & !_LC7_C18;
-- Node name is '|conkeep:u2|:326'
-- Equation name is '_LC8_C20', type is buried
_LC8_C20 = LCELL( _EQ004);
_EQ004 = _LC7_C18
# _LC3_C15 & _LC6_C18
# _LC4_C15 & _LC6_C18
# _LC3_C15 & _LC4_C15
# !_LC3_C15 & !_LC4_C15 & !_LC6_C18;
-- Node name is '|conkeep:u2|~369~1'
-- Equation name is '_LC2_C4', type is buried
-- synthesized logic cell
_LC2_C4 = LCELL( _EQ005);
_EQ005 = _LC4_C15
# _LC6_C18
# _LC3_C15 & _LC7_C18
# !_LC3_C15 & !_LC7_C18;
-- Node name is '|conkeep:u2|:369'
-- Equation name is '_LC7_C4', type is buried
_LC7_C4 = LCELL( _EQ006);
_EQ006 = !_LC6_C4 & _LC7_C4
# reset
# _LC2_C4 & _LC6_C4;
-- Node name is '|conkeep:u2|:378'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ007);
_EQ007 = reset
# _LC1_C8;
-- Node name is '|conkeep:u2|:387'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = LCELL( _EQ008);
_EQ008 = reset
# !_LC3_C2 & _LC6_C4
# _LC4_C2 & !_LC6_C4;
-- Node name is '|conkeep:u2|:396'
-- Equation name is '_LC3_C4', type is buried
_LC3_C4 = LCELL( _EQ009);
_EQ009 = reset
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