translate_1.vhd

来自「电子抢答器 系统复位后进行抢答．超前抢答显示犯规信号」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity translate_1 is port
	(	
	 	en		:in std_logic;
	 	g		:in std_logic_vector(3 downto 0);
	 	b		:out std_logic_vector(3 downto 0)
	);
end translate_1;

architecture t1 of translate_1 is
begin
	process(g,en)
	begin
		if(en='0')then
			b<="0000";
		else
			b(3)<=g(3);
			b(2)<=(not(g(3)) and g(2))or(g(3) and not(g(2)));
			b(1)<=(not(g(3)) and not(g(2)) and g(1))or(not(g(3)) and g(2) and not(g(1)))or(g(3) and not(g(2)) and not(g(1)));
			b(0)<=(not(g(3)) and not(g(2)) and not(g(1)) and g(0))or(not(g(3)) and not(g(2)) and g(1) and not(g(0)))or(not(g(3)) and g(2) and not(g(1)) and not(g(0)))or(g(3) and not(g(2)) and not(g(1)) and not(g(0)))or(not(g(3)) and g(2) and g(1) and g(0))or(g(3) and not(g(2)) and g(1) and g(0))or(g(3) and g(2) and not(g(1)) and g(0))or(g(3) and g(2) and g(1) and not(g(0)));
		end if;
	end process;
end t1;