📄 counter9.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity counter9 is
port(clkin:in std_logic;
qout:out std_logic_vector(6 downto 0);
qou:out std_logic_vector(6 downto 0)
);
end counter9;
architecture counter9 of counter9 is
signal bcd:std_logic_vector(3 downto 0);
signal out1:std_logic_vector(6 downto 0);
signal bc:std_logic_vector(3 downto 0);
signal ou:std_logic_vector(6 downto 0);
begin
process(clkin)
begin
if(clkin'event and clkin='1') then
if(bcd="1010")then
bcd<="0000";
bc<=bc+'1';
if bc="0110" then
bc<="0000";
end if;
else bcd<=bcd+'1';
end if;
case bcd is
when "0000"=>out1<="1111110";
when "0001"=>out1<="0110000";
when "0010"=>out1<="1101101";
when "0011"=>out1<="1111001";
when "0100"=>out1<="0110011";
when "0101"=>out1<="1011011";
when "0110"=>out1<="1011111";
when "0111"=>out1<="1110000";
when "1000"=>out1<="1111111";
when "1001"=>out1<="1111011";
when others=>out1<="1111110";
end case;
case bc is
when "0000"=>ou<="1111110";
when "0001"=>ou<="0110000";
when "0010"=>ou<="1101101";
when "0011"=>ou<="1111001";
when "0100"=>ou<="0110011";
when "0101"=>ou<="1011011";
when others=>ou<="1111110";
end case;
end if;
end process;
qout<=out1;
qou<=ou;
end counter9;
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