📄 c_fenpin2.vhd
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--本程序时钟采用
--40MHz的CLK
--得到一系列
--固定频率的时钟
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c_fenpin2 is
port(clk,trigger,m_signal:in std_logic; --trigger触发信号,m_signal测量信号
fad,fda:out std_logic); --fad采样频率,fda显示频率
end;
architecture behav of c_fenpin2 is
signal c1,f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14:integer;
signal count,timer:integer; --count计数变量,timer定时变量
signal clk1,clk2,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14:std_logic;
signal trig,flag1:std_logic:='0'; --flag1是否测频标志,1不测
--trig触发信号,1触发
begin
--下面两个进程用于测频
--用于定时1S
--clk1为1kHz
process(clk1,trig,flag1)
begin
if trig='0' then
timer<=0;
elsif clk1'event and clk1='1' then
if timer=999 then
flag1<='1';
else
timer<=timer+1;
end if;
end if;
end process;
--用于脉冲计数
process(m_signal,trig,flag1)
begin
if trig='0' then
count<=0;
elsif flag1='1' then
count<=count;
elsif m_signal'event and m_signal='1' then
count<=count+1;
end if;
end process;
--采样频率选择器
process(count)
begin
if flag1='1' then
if count<=2 then
clk2<=y1;
elsif count<=4 then
clk2<=y2;
elsif count<=8 then
clk2<=y3;
elsif count<=16 then
clk2<=y4;
elsif count<=32 then
clk2<=y5;
elsif count<=64 then
clk2<=y6;
elsif count<=128 then
clk2<=y7;
elsif count<=256 then
clk2<=y8;
elsif count<=512 then
clk2<=y9;
elsif count<=1024 then
clk2<=y10;
elsif count<=2048 then
clk2<=y11;
elsif count<=4096 then
clk2<=y12;
elsif count<=8192 then
clk2<=y13;
else
clk2<=y14;
end if;
end if;
end process;
fad<=clk2;
fda<=clk1;
process(trigger)
begin
if trigger'event and trigger='1' then
trig<='1';
end if;
end process;
process(clk,trig)
begin
if trig='0' then
c1<=0;
f1<=0;
f2<=0;
f3<=0;
f4<=0;
f5<=0;
f6<=0;
f7<=0;
f8<=0;
f9<=0;
f10<=0;
f11<=0;
f12<=0;
f13<=0;
f14<=0;
else if clk'event and clk='1' then
if c1=39999 then
c1<=0;
else
c1<=c1+1;
end if;
if f1=999999 then
f1<=0;
else
f1<=f1+1;
end if;
if f2=499999 then
f2<=0;
else
f2<=f2+1;
end if;
if f3=249999 then
f3<=0;
else
f3<=f3+1;
end if;
if f4=124999 then
f4<=0;
else
f4<=f4+1;
end if;
if f5=62499 then
f5<=0;
else
f5<=f5+1;
end if;
if f6=31249 then
f6<=0;
else
f6<=f6+1;
end if;
if f7=15624 then
f7<=0;
else
f7<=f7+1;
end if;
if f8=7811 then
f8<=0;
else
f8<=f8+1;
end if;
if f9=3905 then
f9<=0;
else
f9<=f9+1;
end if;
if f10=1952 then
f10<=0;
else
f10<=f10+1;
end if;
if f11=976 then
f11<=0;
else
f11<=f11+1;
end if;
if f12=487 then
f12<=0;
else
f12<=f12+1;
end if;
if f13=243 then
f13<=0;
else
f13<=f13+1;
end if;
if f14=121 then
f14<=0;
else
f14<=f14+1;
end if;
end if;
end if;
end process;
process(clk)
begin
if trig='1' then
if c1<20000 then
clk1<='0';
else
clk1<='1';
end if;
if f1<500000 then
y1<='0';
else
y1<='1';
end if;
if f2<250000 then
y2<='0';
else
y2<='1';
end if;
if f3<125000 then
y3<='0';
else
y3<='1';
end if;
if f4<62500 then
y4<='0';
else
y4<='1';
end if;
if f5<31250 then
y5<='0';
else
y5<='1';
end if;
if f6<15625 then
y6<='0';
else
y6<='1';
end if;
if f7<7812 then
y7<='0';
else
y7<='1';
end if;
if f8<3906 then
y8<='0';
else
y8<='1';
end if;
if f9<1953 then
y9<='0';
else
y9<='1';
end if;
if f10<976 then
y10<='0';
else
y10<='1';
end if;
if f11<488 then
y11<='0';
else
y11<='1';
end if;
if f12<244 then
y12<='0';
else
y12<='1';
end if;
if f13<122 then
y13<='0';
else
y13<='1';
end if;
if f14<61 then
y14<='0';
else
y14<='1';
end if;
end if;
end process;
end;
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