c_fenpin1.vhd

来自「cpld数据采集测频」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity c_fenpin1 is
    port(clk:in std_logic;
         y:out std_logic);
          
end;

architecture behav of c_fenpin1 is
   signal fpq:integer;
   signal k,n1:std_logic_vector(6 downto 0);
   signal y1,clk1:std_logic;
   
begin

process(clk)
  begin
  if clk'event and clk='1' then
     if fpq=15 then
        fpq<=0;
     else 
        fpq<=fpq+1;
     end if;
  end if;
end process;
  
process(clk)
  begin
         if fpq<8 then
             y1<='0';
         else
             y1<='1';
         end if;
 end process;   

  y<=y1;
          

end;