c_fenpin5.vhd

cpld数据采集测频

--本程序时钟采用
--40MHz的CLK
--得到一系列
--固定频率的时钟
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity c_fenpin5 is
    port(clk,trigger,m_signal:in std_logic; --trigger触发信号，m_signal测量信号
             fad,fda:out std_logic);   --fad采样频率，fda显示频率
          
end;

architecture behav of c_fenpin5 is
   signal count:std_logic_vector(15 downto 0);    --count计数变量
   signal timer:std_logic_vector(10 downto 0);
   signal fvalue:std_logic_vector(19 downto 0);
   signal clk1,clk2:std_logic;
   signal trig,flag1:std_logic:='0';   --flag1是否测频标志，1不测
                                       --trig触发信号，1触发
begin

process(trigger)
    begin
        if trigger'event and trigger='1'  then
            trig<='1';
        end if;
end process;

--下面两个进程用于测频
--用于定时1S
--clk1为1kHz
process(clk1,trig,flag1)
    begin
        if trig='0' then
            timer<="00000000000";
        elsif clk1'event and clk1='1' then
            if timer="10011000100" then
                flag1<='1';
            else
                timer<=timer+1;
            end if;
        end if;
    end process;
--用于脉冲计数
process(m_signal,trig,flag1)
    begin
        if trig='0' then
            count<="0000000000000000";
        elsif flag1='1' then
            count<=count;
        elsif m_signal'event and m_signal='1' then
            count<=count+1;
        end if;
end process;


-- 得到一系列分频系数为2^n 的时钟频率
process(clk)
    begin
        if trig='0' then
            fvalue<="00000000000000000000";
        elsif clk'event and clk='1' then
            fvalue<=fvalue+1;
        end if;
end process; 


--采样频率选择器
process(count)
    begin 
        if flag1='1' then
            if count<="0000000000000010" then
                clk2<=fvalue(19);
            elsif  count<="0000000000000100" then
                clk2<=fvalue(18);
            elsif  count<="0000000000001000" then
                clk2<=fvalue(17);
            elsif  count<="0000000000010000" then
                clk2<=fvalue(16);
            elsif  count<="0000000000100000" then
                clk2<=fvalue(15);
            elsif  count<="0000000001000000" then
                clk2<=fvalue(14);
            elsif  count<="0000000010000000" then
                clk2<=fvalue(13);
            elsif  count<="0000000100000000" then
                clk2<=fvalue(12);
            elsif  count<="0000001000000000" then
                clk2<=fvalue(11);
            elsif  count<="0000010000000000" then
                clk2<=fvalue(10);
            elsif  count<="0000100000000000" then
                clk2<=fvalue(9);
            elsif  count<="0001000000000000" then
                clk2<=fvalue(8);
            elsif  count<="0010000000000000" then
                clk2<=fvalue(7);
            else 
                clk2<=fvalue(6);
            end if;
       end if;
end process;

fad<=clk2;

clk1<=fvalue(14);
fda<=fvalue(14);
    
end;