control.vhd

cpld数据采集测频

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity control is
    port(fad,fda,channal:in std_logic;    --channal为0，选择通道1；为1，选择通道2
         add1,add2:out std_logic_vector(10 downto 0));  --y为RAM的输入地址
          
end;

architecture behav of control is
signal y1,y2:std_logic_vector(10 downto 0); 
constant addoff:std_logic_vector(10 downto 0):="01010000000";     
begin

process(fad)
  begin
  if fad'event and fad='1' then
     if y1="010011111111" then
        y1<="00000000000";
     else 
        y1<=y1+1;
     end if;
  end if;
end process;

process(fda)
  begin
  if fda'event and fda='1' then
     if y2="010011111111" then
        y2<="00000000000";
     else 
        y2<=y2+1;
     end if;
  end if;
end process;

process
    begin
        if channal='0' then
            add1<=y1;             --add1写入地址
            add2<=y2;             --add2读出地址
        else
            add1<=y1+addoff;
            add2<=y2+addoff;
        end if;
end process;          

end;