echo_cancel.v

verilog写的回波抵消程序

 
assign x_o = {x_v_s,x_v,x_e_s,x_e};
endmodule


module valuedeal(in20,out10,out4_e,clk);
input clk;
input[19:0] in20;
output[9:0] out10;
output[3:0] out4_e;
reg[19:0] A,D;
reg[9:0] B;
reg[3:0] C;

always @(posedge clk)
 begin
   A = in20;
     if (A < 1024)
       begin
        B = A[9:0];
        C = 0;   //0~1023，维持
       end
      if ((A < 10240) && (A >= 1024))
       begin
        D = A/10;  
        B = D[9:0];
        C = 1;
       end
      if ((A < 102400) && (A >= 10240))
       begin
        D = A/100;
        B = D[9:0];
        C = 2;
       end
      if ((A < 1024000) && (A >= 102400))
       begin
        D = A/1000;
        B = D[9:0];
        C = 3;
       end
      if ((A < 1048576) && (A >= 1024000))
       begin
        D = A/10000;
        B = D[9:0];
        C = 4;  //共分五段处理，防止值乘后溢出
       end
 end
assign out10 = B;
assign out4_e = C;
endmodule


module expdeal(a_s,b_s,a,b,c,x_s,x,clk);
input a_s,b_s,clk;
output x_s;
input[3:0] a,b,c;
output[3:0] x;
reg xs;
reg[1:0] ds;
reg[5:0] xr;
always @(posedge clk)
 begin
  xr = a+b+c;
  ds = a_s+b_s;
    if (ds == 0)
       xs = 0;
    else if (ds == 1) 
       if (xr[4] == 0)
          xs = 1;
       else   xs = 0;
    else if (ds == 2)
       if (xr[5] == 0)
          xs = 1;
       else   xs = 0;
 end
assign x_s = xs;
assign x = xr[3:0];
endmodule


module multiply(a,b,x_20,clk); //十位乘法器
input [9:0] a,b;
input clk;
output [19:0] x_20;
reg[18:0] a_temp;
reg[17:0] a_temp1;
reg[16:0] a_temp2;
reg[15:0] a_temp3;
reg[14:0] a_temp4;
reg[13:0] a_temp5;
reg[12:0] a_temp6;
reg[11:0] a_temp7;
reg[10:0] a_temp8;
reg[9:0] a_temp9;
wire[9:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,a10;
wire[19:0] x_20;
wire[18:0] out1,c1;
wire[16:0] out2;
wire[14:0] out3,c2;
wire[12:0] out4;
wire[10:0] out5;

assign out1 = a_temp + a_temp1;
assign out2 = a_temp2 + a_temp3;
assign out3 = a_temp4 + a_temp5;
assign out4 = a_temp6 + a_temp7;
assign out5 = a_temp8 + a_temp9;
assign c1 = out1 + out2;
assign c2 = out3 + out4;
assign x_20 = c1 + c2 + out5;


  mul101       m1 (a,b[9],a1);
  mul101       m2 (a,b[8],a2);
  mul101       m3 (a,b[7],a3);
  mul101       m4 (a,b[6],a4);
  mul101       m5 (a,b[5],a5);
  mul101       m6 (a,b[4],a6);
  mul101       m7 (a,b[3],a7);
  mul101       m8 (a,b[2],a8);
  mul101       m9 (a,b[1],a9);
  mul101       m10 (a,b[0],a10);
always @(posedge clk)
 begin
  a_temp[8:0] = 9'b000000000;
  a_temp[18:9] = a1;
  a_temp1[7:0] = 8'b00000000;
  a_temp1[17:8] = a2;
  a_temp2[6:0] = 7'b0000000;
  a_temp2[16:7] = a3;
  a_temp3[5:0] = 6'b000000;
  a_temp3[15:6] = a4;
  a_temp4[4:0] = 5'b00000;
  a_temp4[14:5] = a5;
  a_temp5[3:0] = 4'b0000;
  a_temp5[13:4] = a6;
  a_temp6[2:0] = 3'b000;
  a_temp6[12:3] = a7;
  a_temp7[1:0] = 2'b00;
  a_temp7[11:2] = a8;
  a_temp8[0] = 1'b0;
  a_temp8[10:1] = a9;
  a_temp9[9:0] = a10;
 end
endmodule


module mul101(operand,sel,out10);
input[9:0] operand;
input sel;
output[9:0] out10;
assign out10 = (sel) ? (operand) : 10'b0000000000;
endmodule


/*
调整模块，精度十分位
by dingjin 

*/
module adjust(ina,outb,clk);
input[15:0] ina;
output[15:0] outb;
input clk;
reg a_v_s,a_e_s;
reg[9:0] a_v;
reg[3:0] a_e;
reg[14:0] b_v;
reg[7:0] rcount;
reg[15:0] temp;
integer v;

always @(posedge clk)
 begin
  a_v_s = ina[15];
  a_v = ina[14:5];
  a_e_s = ina[4];
  a_e = ina[3:0];

  if (a_e_s == 0)
    begin
      rcount = a_e + 1;
      if (rcount == 0)
      v = 1;
      if (rcount == 1)
      v = 10;
      if (rcount == 2)
      v = 100;
      if (rcount == 3)
      v = 1000;
      if (rcount == 4)
      v = 10000;
      temp = a_v * v;      
      b_v = temp[14:0];
    end
  if (a_e_s == 1)
    begin    
      rcount[2:0] = 1111 - a_e;   
      if (rcount == 0)
      begin
      temp[9:0] = a_v;
      temp[15:10] = 6'b000000;
      end
      if (rcount == 1)
      begin
      temp[6:0] = a_v/10;
      temp[15:7] = 9'b000000000;
      end
      if (rcount == 2)
      begin
      temp[3:0] = a_v/100;
      temp[15:4] = 12'b000000000000;
      end
      if (rcount == 3)
      begin
      temp[0] = a_v/1000;
      temp[15:1] = 15'b000000000000000;
      end
      if (rcount == 4)
      temp = 0;     
      b_v = temp[14:0];
    end    
 end         
         

 assign outb = {a_v_s,b_v};
endmodule


/*
无符号调整模块，精度1
by dingjin 

*/
module adjust1(ina,outb,clk);
input[15:0] ina;
output[15:0] outb;
input clk;
reg a_v_s,a_e_s;
reg[9:0] a_v;
reg[3:0] a_e;
reg[15:0] b_v;
reg[7:0] rcount;
reg[15:0] temp;
integer v;

always @(posedge clk)
 begin
  a_v_s = ina[15];
  a_v = ina[14:5];
  a_e_s = ina[4];
  a_e = ina[3:0];

  if (a_e_s == 0)
    begin
      rcount = a_e;
      if (rcount == 0)
      v = 1;
      if (rcount == 1)
      v = 10;
      if (rcount == 2)
      v = 100;
      if (rcount == 3)
      v = 1000;
      if (rcount == 4)
      v = 10000;
      b_v = a_v * v;      
    end
  if (a_e_s == 1)
    begin    
      rcount[2:0] = 1111 - a_e;   
      if (rcount == 0)
      begin
      temp[6:0] = a_v/10;
      temp[15:7] = 9'b000000000;
      end
      if (rcount == 1)
      begin
      temp[3:0] = a_v/100;
      temp[15:4] = 12'b000000000000;
      end
      if (rcount == 2)
      begin
      temp[0] = a_v/1000;
      temp[15:1] = 15'b000000000000000;
      end
      if (rcount == 3)
      temp = 0;     
      b_v = temp;
    end    
 end         
         

 assign outb = b_v;
endmodule


module adjust1_r(ina,outb,clk);
input[15:0] ina;
output[15:0] outb;
input clk;
reg[15:0] rin;
reg[9:0] b_v,temp;
reg[3:0] b_e;

always @(posedge clk)
 begin
  rin = ina;
   if (rin < 1024)
    begin
     temp = rin[9:0];
     b_e = 4'b0000;
    end
   if ((rin < 10240) && (rin >= 1024))
    begin
     temp = rin/10;
     b_e = 4'b0001;
    end
   if (rin >= 10240)
    begin
     temp = rin/100;
     b_e = 4'b0010;
    end
  b_v = temp;
 end

assign outb = {0,b_v,0,b_e};
endmodule


module adjust_r(ina,outb,clk);
input[15:0] ina;
output[15:0] outb;
input clk;
reg[14:0] a_v;
reg a_s;
reg[9:0] temp;
reg[9:0] b_v;
reg[4:0] b_e;

always @(posedge clk)
 begin
  a_s = ina[15];
  a_v = ina[14:0];
    if (a_v < 1024)
    begin
     temp = a_v[9:0];
     b_e = 5'b11111;
    end
   if ((a_v < 10240) && (a_v >= 1024))
    begin
     temp = a_v/10;
     b_e = 5'b00000;
    end
   if (a_v >= 10240)
    begin
     temp = a_v/100;
     b_e = 5'b00001;
    end
  b_v = temp;
 end

assign outb = {a_s,b_v,b_e}; 
endmodule


/*
调整模块，精度万分位
by dingjin 

*/
module adjust2(ina,outb,clk);
input[15:0] ina;
output[15:0] outb;
input clk;
reg a_v_s,a_e_s;
reg[9:0] a_v;
reg[3:0] a_e;
reg[14:0] b_v;
reg[7:0] rcount;
reg[15:0] temp;
integer v;

always @(posedge clk)
 begin
  a_v_s = ina[15];
  a_v = ina[14:5];
  a_e_s = ina[4];
  a_e = ina[3:0];

  if (a_e_s == 0)
    begin
      rcount = a_e + 4;
      if (rcount == 4)
      v = 10000;
      temp = a_v * v;      
      b_v = temp[14:0];
    end
  if (a_e_s == 1)
    begin    
     if ((a_e >= 1100) && (a_e <= 1111))
      begin
       rcount[1:0] = 1111 - a_e;   
       if (rcount == 3)
       temp = a_v;
       if (rcount == 2)
       temp = a_v * 10;
       if (rcount == 1)
       temp = a_v * 100;
       if (rcount == 0)
       temp = a_v * 1000;
      end
     if (a_e < 1100)
      begin
       rcount[2:0] = 1100 - a_e;   
       if (rcount == 1)
       begin
       temp[6:0] = a_v/10;
       temp[15:7] = 9'b000000000;
       end
       if (rcount == 2)
       begin
       temp[3:0] = a_v/100;
       temp[15:4] = 12'b000000000000;
       end
       if (rcount == 3)
       begin
       temp[0] = a_v/1000;
       temp[15:1] = 15'b000000000000000;
       end
       if (rcount == 4)
       temp = 0;     
      end 
     b_v = temp[14:0];
    end
 end         
         

 assign outb = {a_v_s,b_v};
endmodule


module adjust2_r(ina,outb,clk);
input[15:0] ina;
output[15:0] outb;
input clk;
reg[14:0] a_v;
reg a_s;
reg[9:0] temp;
reg[9:0] b_v;
reg[4:0] b_e;

always @(posedge clk)
 begin
  a_s = ina[15];
  a_v = ina[14:0];
    if (a_v < 1024)
    begin
     temp = a_v[9:0];
     b_e = 5'b11100;
    end
   if ((a_v < 10240) && (a_v >= 1024))
    begin
     temp = a_v/10;
     b_e = 5'b11101;
    end
   if (a_v >= 10240)
    begin
     temp = a_v/100;
     b_e = 5'b11110;
    end
  b_v = temp;
 end

assign outb = {a_s,b_v,b_e}; 
endmodule