echo_cancel.v

verilog写的回波抵消程序

module echo_cancel(in,out,clk);
input[7:0] in;
input clk;
output[7:0] out;
reg[7:0] x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,rout;
reg[15:0] H1_10,H2_10,H3_10,H4_10,H5_10,H6_10,H7_10,H8_10,dn,yn,en,delta10,delta9;
reg[15:0] H1_9,H2_9,H3_9,H4_9,H5_9,H6_9,H7_9,H8_9,delta10_reci,v1,v2,v3,v4,v5;
reg[15:0] v2_ad,v3_ad,delta10_ad,en_adr,v_x8,v_x7,v_x6,v_x5,v_x4,v_x3,v_x2,v_x1;
reg[14:0] ren,temp,temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8;
reg[15:0] v_x8_ad,v_x7_ad,v_x6_ad,v_x5_ad,v_x4_ad,v_x3_ad,v_x2_ad,v_x1_ad;
reg[15:0] H1_9_ad,H2_9_ad,H3_9_ad,H4_9_ad,H5_9_ad,H6_9_ad,H7_9_ad,H8_9_ad;
reg[15:0] H1_10_ad,H2_10_ad,H3_10_ad,H4_10_ad,H5_10_ad,H6_10_ad,H7_10_ad,H8_10_ad;
reg[8:0] enout;
integer i;
parameter u = 0010011100011100,alfa = 0000000000111110,alfa1 = 0000110001111110;

always @(posedge clk)
 begin
   i = i + 1;
    if (i == 1000)
      begin
       i = 0;      
       x10 <= in;
       x9 <= x10;
       x8 <= x9;
       x7 <= x8;
       x6 <= x7;
       x5 <= x6;
       x4 <= x5;
       x3 <= x4;
       x2 <= x3;
       x1 <= x2;
       delta9 <= delta10;
       H1_9 <= H1_10;
       H2_9 <= H2_10;
       H3_9 <= H3_10;
       H4_9 <= H4_10;
       H5_9 <= H5_10;
       H6_9 <= H6_10;
       H7_9 <= H7_10;
       H8_9 <= H8_10;
      end
 end

make_echo m_e(x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,dn,clk); 
adaptive_filter a_f(x10,x9,x8,x7,x6,x5,x4,x3,H1_10,H2_10,H3_10,H4_10,H5_10,H6_10,H7_10,H8_10,yn,clk);
 
always @(posedge clk)
 begin
   temp = dn[14:0] - yn[14:0];
   if (temp[14] == 0)
    begin
     en[15] = 0;
     en[14:0] = temp;
    end 
   if (temp[14] == 1)
     begin
       ren = ~(temp[14:0] - 1);
       en[15] = 1;
       en[14:0] = ren;
     end
 end

always @(posedge clk)
 begin
   enout[7:0] = en[14:0]/10;
   enout[8] = en[15];
 end

my_fpmul fp21(alfa,x10,clk,v1);
my_fpmul fp22(v1,x10,clk,v2);
my_fpmul fp23(alfa1,delta9,clk,v3);
adjust1 ad1_1(v2,v2_ad,clk);
adjust1 ad1_2(v3,v3_ad,clk);
adjust_r adr(en,en_adr,clk);

always @(posedge clk)
 begin
  delta10_ad = v2_ad + v3_ad;
    if (delta10_ad <= 500)
      delta10_reci = 0000000000111110;
    if ((delta10_ad > 500) && (delta10_ad <=5000))
      delta10_reci = 0000000000111101;      
    if (delta10_ad > 5000)
      delta10_reci = 0000000000111100;
 end

adjust1_r ad1r(delta10_ad,delta10,clk);
my_fpmul fp24(u,delta10_reci,clk,v4);
my_fpmul fp25(v4,en_adr,clk,v5);
my_fpmul fp31(v5,x3,clk,v_x1);
my_fpmul fp32(v5,x4,clk,v_x2);
my_fpmul fp33(v5,x5,clk,v_x3);
my_fpmul fp34(v5,x6,clk,v_x4);
my_fpmul fp35(v5,x7,clk,v_x5);
my_fpmul fp36(v5,x8,clk,v_x6);
my_fpmul fp37(v5,x9,clk,v_x7);
my_fpmul fp38(v5,x10,clk,v_x8);
adjust2 ad2_8(v_x8,v_x8_ad,clk);
adjust2 ad2_7(v_x7,v_x7_ad,clk);
adjust2 ad2_6(v_x6,v_x6_ad,clk);
adjust2 ad2_5(v_x5,v_x5_ad,clk);
adjust2 ad2_4(v_x4,v_x4_ad,clk);
adjust2 ad2_3(v_x3,v_x3_ad,clk);
adjust2 ad2_2(v_x2,v_x2_ad,clk);
adjust2 ad2_1(v_x1,v_x1_ad,clk);
adjust2 ad2_18(H8_9,H8_9_ad,clk);
adjust2 ad2_17(H7_9,H7_9_ad,clk);
adjust2 ad2_16(H6_9,H6_9_ad,clk);
adjust2 ad2_15(H5_9,H5_9_ad,clk);
adjust2 ad2_14(H4_9,H4_9_ad,clk);
adjust2 ad2_13(H3_9,H3_9_ad,clk);
adjust2 ad2_12(H2_9,H2_9_ad,clk);
adjust2 ad2_11(H1_9,H1_9_ad,clk);

always @(posedge clk)
 begin
  if (v_x8_ad[15] == 0)
  H1_10_ad[14:0] = H1_9_ad[14:0] + v_x8_ad[14:0]; 
  if (v_x7_ad[15] == 0)   
  H2_10_ad[14:0] = H2_9_ad[14:0] + v_x7_ad[14:0];  
  if (v_x6_ad[15] == 0)    
  H3_10_ad[14:0] = H3_9_ad[14:0] + v_x6_ad[14:0];
  if (v_x5_ad[15] == 0)      
  H4_10_ad[14:0] = H4_9_ad[14:0] + v_x5_ad[14:0];      
  if (v_x4_ad[15] == 0)
  H5_10_ad[14:0] = H5_9_ad[14:0] + v_x4_ad[14:0];      
  if (v_x3_ad[15] == 0)
  H6_10_ad[14:0] = H6_9_ad[14:0] + v_x3_ad[14:0];      
  if (v_x2_ad[15] == 0)
  H7_10_ad[14:0] = H7_9_ad[14:0] + v_x2_ad[14:0];      
  if (v_x1_ad[15] == 0)
  H8_10_ad[14:0] = H8_9_ad[14:0] + v_x1_ad[14:0];  
  if (v_x8_ad[15] == 1)
  begin
  temp1 = H1_9_ad[14:0] - v_x8_ad[14:0]; 
    if (temp1[14] == 1)
       H1_10_ad[14:0] = 0;
    else H1_10_ad[14:0] = temp1;
  end
  if (v_x7_ad[15] == 1)
  begin
  temp2 = H2_9_ad[14:0] - v_x7_ad[14:0]; 
    if (temp2[14] == 1)
       H2_10_ad[14:0] = 0;
    else H2_10_ad[14:0] = temp2;
  end
  if (v_x6_ad[15] == 1)
  begin
  temp3 = H3_9_ad[14:0] - v_x6_ad[14:0]; 
    if (temp3[14] == 1)
       H3_10_ad[14:0] = 0;
    else H3_10_ad[14:0] = temp3;
  end
  if (v_x5_ad[15] == 1)
  begin
  temp4 = H4_9_ad[14:0] - v_x5_ad[14:0]; 
    if (temp4[14] == 1)
       H4_10_ad[14:0] = 0;
    else H4_10_ad[14:0] = temp4;
  end
  if (v_x4_ad[15] == 1)
  begin
  temp5 = H5_9_ad[14:0] - v_x4_ad[14:0]; 
    if (temp5[14] == 1)
       H5_10_ad[14:0] = 0;
    else H5_10_ad[14:0] = temp5;
  end
  if (v_x3_ad[15] == 1)
  begin
  temp6 = H6_9_ad[14:0] - v_x3_ad[14:0]; 
    if (temp6[14] == 1)
       H6_10_ad[14:0] = 0;
    else H6_10_ad[14:0] = temp6;
  end
  if (v_x2_ad[15] == 1)
  begin
  temp7 = H7_9_ad[14:0] - v_x2_ad[14:0]; 
    if (temp7[14] == 1)
       H7_10_ad[14:0] = 0;
    else H7_10_ad[14:0] = temp7;
  end
  if (v_x1_ad[15] == 1)
  begin
  temp8 = H8_9_ad[14:0] - v_x1_ad[14:0]; 
    if (temp8[14] == 1)
       H8_10_ad[14:0] = 0;
    else H8_10_ad[14:0] = temp8;
  end
 H1_10_ad[15] = 0; 
 H2_10_ad[15] = 0; 
 H3_10_ad[15] = 0; 
 H4_10_ad[15] = 0; 
 H5_10_ad[15] = 0; 
 H6_10_ad[15] = 0; 
 H7_10_ad[15] = 0; 
 H8_10_ad[15] = 0; 
 end    
  
adjust2_r ad2r_1(H1_10_ad,H1_10,clk);
adjust2_r ad2r_2(H2_10_ad,H2_10,clk);
adjust2_r ad2r_3(H3_10_ad,H3_10,clk);
adjust2_r ad2r_4(H4_10_ad,H4_10,clk);
adjust2_r ad2r_5(H5_10_ad,H5_10,clk);
adjust2_r ad2r_6(H6_10_ad,H6_10,clk);
adjust2_r ad2r_7(H7_10_ad,H7_10,clk);
adjust2_r ad2r_8(H8_10_ad,H8_10,clk);

always @(posedge clk)
 begin
  if (enout[8] == 0)
    rout = x10 + enout[7:0];
  if (enout[8] == 1)
    rout = x10 - enout[7:0];
 end

assign out = rout;
endmodule
    

module adaptive_filter(in8,in7,in6,in5,in4,in3,in2,in1,f1,f2,f3,f4,f5,f6,f7,f8,out,clk);
input[7:0] in8,in7,in6,in5,in4,in3,in2,in1;
input[15:0] f1,f2,f3,f4,f5,f6,f7,f8;
output[15:0] out;
input clk;
reg[15:0] x8,x7,x6,x5,x4,x3,x2,x1,fout;
reg[15:0] H1,H2,H3,H4,H5,H6,H7,H8;
integer i;

always @(posedge clk)
 begin 
  x8[15:13] = 3'b000;
  x8[12:5] = in8;
  x8[4:0] = 5'b00000;
  x7[15:13] = 3'b000;
  x7[12:5] = in7;
  x7[4:0] = 5'b00000;
  x6[15:13] = 3'b000;
  x6[12:5] = in6;
  x6[4:0] = 5'b00000;
  x5[15:13] = 3'b000;
  x5[12:5] = in5;
  x5[4:0] = 5'b00000;
  x4[15:13] = 3'b000;
  x4[12:5] = in4;
  x4[4:0] = 5'b00000;
  x3[15:13] = 3'b000;
  x3[12:5] = in3;
  x3[4:0] = 5'b00000;
  x2[15:13] = 3'b000;
  x2[12:5] = in2;
  x2[4:0] = 5'b00000;
  x1[15:13] = 3'b000;
  x1[12:5] = in1;
  x1[4:0] = 5'b00000;
  H1 = f1;
  H2 = f2;
  H3 = f3;
  H4 = f4;
  H5 = f5;
  H6 = f6;
  H7 = f7;
  H8 = f8;
 end
 
juanji8 jj8(x8,x7,x6,x5,x4,x3,x2,x1,H1,H2,H3,H4,H5,H6,H7,H8,fout,clk);

assign out = fout;
endmodule  
         
module juanji8(c8,c7,c6,c5,c4,c3,c2,c1,y1,y2,y3,y4,y5,y6,y7,y8,out,clk);      
input[15:0] c8,c7,c6,c5,c4,c3,c2,c1,y1,y2,y3,y4,y5,y6,y7,y8;
input clk;
output[15:0] out;
reg[15:0]  rc8,rc7,rc6,rc5,rc4,rc3,rc2,rc1,ry1,ry2,ry3,ry4,ry5,ry6,ry7,ry8;
reg[15:0]  sum1,sum2,sum3,sum4,sum5,sum6,sum7,sum8;
reg[15:0]  sum1_ad,sum2_ad,sum3_ad,sum4_ad,sum5_ad,sum6_ad,sum7_ad,sum8_ad;
reg[15:0]  sum11,sum12,sum13,sum14,sum15,sum16,sum;


always @(posedge clk)
 begin
   rc8 = c8;
   rc7 = c7;
   rc6 = c6;
   rc5 = c5;
   rc4 = c4;
   rc3 = c3;
   rc2 = c2;
   rc1 = c1;
   ry8 = y8;
   ry7 = y7;
   ry6 = y6;
   ry5 = y5;
   ry4 = y4;
   ry3 = y3;
   ry2 = y2;
   ry1 = y1;   
 end

my_fpmul fp11(rc8,ry1,clk,sum1);
my_fpmul fp12(rc7,ry2,clk,sum2);
my_fpmul fp13(rc6,ry3,clk,sum3);
my_fpmul fp14(rc5,ry4,clk,sum4);
my_fpmul fp15(rc4,ry5,clk,sum5);
my_fpmul fp16(rc3,ry6,clk,sum6);
my_fpmul fp17(rc2,ry7,clk,sum7);
my_fpmul fp18(rc1,ry8,clk,sum8);
adjust ad11(sum8,sum8_ad,clk);
adjust ad12(sum7,sum7_ad,clk);
adjust ad13(sum6,sum6_ad,clk);
adjust ad14(sum5,sum5_ad,clk);
adjust ad15(sum4,sum4_ad,clk);
adjust ad16(sum3,sum3_ad,clk);
adjust ad17(sum2,sum2_ad,clk);
adjust ad18(sum1,sum1_ad,clk);

always @(posedge clk)
 begin
   sum11 = sum1_ad[14:0] + sum2_ad[14:0];
   sum12 = sum3_ad[14:0] + sum4_ad[14:0];
   sum13 = sum5_ad[14:0] + sum6_ad[14:0];
   sum14 = sum7_ad[14:0] + sum8_ad[14:0];
   sum15 = sum11 + sum12;
   sum16 = sum13 + sum14;
   sum = sum15 + sum16;
 end    

assign out = sum;
endmodule


module make_echo(in10,in9,in8,in7,in6,in5,in4,in3,in2,in1,out,clk);
input[7:0] in10,in9,in8,in7,in6,in5,in4,in3,in2,in1;
output[15:0] out;
input clk;
reg[15:0] x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,echo;
integer i;

always @(posedge clk)
 begin 
  x10[15:13] = 3'b000;
  x10[12:5] = in10;
  x10[4:0] = 5'b00000;
  x9[15:13] = 3'b000;
  x9[12:5] = in9;
  x9[4:0] = 5'b00000;
  x8[15:13] = 3'b000;
  x8[12:5] = in8;
  x8[4:0] = 5'b00000;
  x7[15:13] = 3'b000;
  x7[12:5] = in7;
  x7[4:0] = 5'b00000;
  x6[15:13] = 3'b000;
  x6[12:5] = in6;
  x6[4:0] = 5'b00000;
  x5[15:13] = 3'b000;
  x5[12:5] = in5;
  x5[4:0] = 5'b00000;
  x4[15:13] = 3'b000;
  x4[12:5] = in4;
  x4[4:0] = 5'b00000;
  x3[15:13] = 3'b000;
  x3[12:5] = in3;
  x3[4:0] = 5'b00000;
  x2[15:13] = 3'b000;
  x2[12:5] = in2;
  x2[4:0] = 5'b00000;
  x1[15:13] = 3'b000;
  x1[12:5] = in1;
  x1[4:0] = 5'b00000;
 end
 
juanji10 jj10(x10,x9,x8,x7,x6,x5,x4,x3,x2,x1,echo,clk);

assign out = echo;
endmodule  
         
module juanji10(c10,c9,c8,c7,c6,c5,c4,c3,c2,c1,outecho,clk);      
parameter h1 = 16'b0000000001011110,h2 = 16'b0000000000111110,h3 = 16'b0000000111111101,
          h4 = 16'b0000000100011101,h5 = 16'b0000000010111101,h6 = 16'b0000000010111101,
          h7 = 16'b0000000100011101,h8 = 16'b0000000111111101,h9 = 16'b0000000000111110,
          h10 = 16'b0000000001011110;
//h1=0.02,h2=0.01,h3=0.015,h4=0.008,h5=0.005成线性
input[15:0] c10,c9,c8,c7,c6,c5,c4,c3,c2,c1;
input clk;
output[15:0] outecho;
reg[15:0]  rc10,rc9,rc8,rc7,rc6,rc5,rc4,rc3,rc2,rc1;
reg[15:0]  sum1,sum2,sum3,sum4,sum5,sum6,sum7,sum8,sum9,sum10;
reg[15:0]  sum1_ad,sum2_ad,sum3_ad,sum4_ad,sum5_ad,sum6_ad,sum7_ad,sum8_ad,sum9_ad,sum10_ad;
reg[15:0]  sum11,sum12,sum13,sum14,sum15,sum16,sum17,sum;


always @(posedge clk)
 begin
   rc10 = c10;
   rc9 = c9;
   rc8 = c8;
   rc7 = c7;
   rc6 = c6;
   rc5 = c5;
   rc4 = c4;
   rc3 = c3;
   rc2 = c2;
   rc1 = c1;
 end

my_fpmul fp1(rc10,h1,clk,sum1);
my_fpmul fp2(rc9,h2,clk,sum2);
my_fpmul fp3(rc8,h3,clk,sum3);
my_fpmul fp4(rc7,h4,clk,sum4);
my_fpmul fp5(rc6,h5,clk,sum5);
my_fpmul fp6(rc5,h6,clk,sum6);
my_fpmul fp7(rc4,h7,clk,sum7);
my_fpmul fp8(rc3,h8,clk,sum8);
my_fpmul fp9(rc2,h9,clk,sum9);
my_fpmul fp10(rc1,h10,clk,sum10);
adjust ad1(sum10,sum10_ad,clk);
adjust ad2(sum9,sum9_ad,clk);
adjust ad3(sum8,sum8_ad,clk);
adjust ad4(sum7,sum7_ad,clk);
adjust ad5(sum6,sum6_ad,clk);
adjust ad6(sum5,sum5_ad,clk);
adjust ad7(sum4,sum4_ad,clk);
adjust ad8(sum3,sum3_ad,clk);
adjust ad9(sum2,sum2_ad,clk);
adjust ad10(sum1,sum1_ad,clk);

always @(posedge clk)
 begin
   sum11 = sum1_ad[14:0] + sum2_ad[14:0];
   sum12 = sum3_ad[14:0] + sum4_ad[14:0];
   sum13 = sum5_ad[14:0] + sum6_ad[14:0];
   sum14 = sum7_ad[14:0] + sum8_ad[14:0];
   sum15 = sum9_ad[14:0] + sum10_ad[14:0];
   sum16 = sum11 + sum12;
   sum17 = sum13 + sum14;
   sum = sum15 + sum16 + sum17;
 end    

assign outecho = sum;
endmodule


/*我定义了数据格式，16位，一位值符号，十位值，一位指数符号，四位值数。
例如200=0000000001000010；-0.005=1000000010110011。
程序分四块处理，值符号位10clk左右搞定，指数部分15clk左右搞定，值部分20-45clk搞定，
我试了最繁琐的情况，45clk肯定能搞定。
fp_mul v1.0 by dingjin
*/
module my_fpmul(a_i,b_i,clk,x_o);
input[15:0] a_i,b_i;
input clk;
output[15:0] x_o;
reg[19:0] x20_v;
reg a_v_s,a_e_s,b_v_s,b_e_s,x_v_s,x_e_s;
reg[9:0] a_v,b_v,x_v;
reg[3:0] a_e,b_e,x_e,x4_e; 
//把16位被乘数乘数分成四段，分别为值符号、值、指数符号、指数
 
always @(posedge clk)
begin
 a_v_s = a_i[15];
 b_v_s = b_i[15];
 a_v = a_i[14:5];
 b_v = b_i[14:5];
 a_e_s = a_i[4];
 b_e_s = b_i[4];
 a_e = a_i[3:0];
 b_e = b_i[3:0];


 x_v_s = a_v_s ^ b_v_s; //值符号处理
end
 multiply     mul (a_v,b_v,x20_v,clk);    //值处理
 valuedeal vd (x20_v,x_v,x4_e,clk);    //直指数转换
 expdeal ed (a_e_s,b_e_s,a_e,b_e,x4_e,x_e_s,x_e,clk);
//指数处理