cf_fp_mul_p_8_23.v

verilog浮点乘发器

module cf_fp_mul_p_8_23_32 (i1, i2, o1, o2);
input  [8:0] i1;
input  [30:0] i2;
output [8:0] o1;
output [29:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   [8:0] n5;
wire   [8:0] n6;
wire   [8:0] n7;
wire   [29:0] n8;
wire   [29:0] n9;
wire   [29:0] n10;
wire   s11_1;
wire   s12_1;
wire   s12_2;
wire   s12_3;
wire   s12_4;
wire   s12_5;
wire   s12_6;
wire   s12_7;
wire   s12_8;
wire   s12_9;
assign n1 = i2[30];
assign n2 = ~s11_1;
assign n3 = n1 | n2;
assign n4 = ~n3;
assign n5 = 9'b000000001;
assign n6 = i1 - n5;
assign n7 = n4 ? n6 : i1;
assign n8 = {i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n9 = {i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n10 = n4 ? n8 : n9;
cf_fp_mul_p_8_23_49 s11 (s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9, s11_1);
cf_fp_mul_p_8_23_60 s12 (i1, s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9);
assign o2 = n10;
assign o1 = n7;
endmodule

module cf_fp_mul_p_8_23_33 (i1, i2, o1, o2);
input  [8:0] i1;
input  [31:0] i2;
output [8:0] o1;
output [30:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   [8:0] n5;
wire   [8:0] n6;
wire   [8:0] n7;
wire   [30:0] n8;
wire   [30:0] n9;
wire   [30:0] n10;
wire   s11_1;
wire   s12_1;
wire   s12_2;
wire   s12_3;
wire   s12_4;
wire   s12_5;
wire   s12_6;
wire   s12_7;
wire   s12_8;
wire   s12_9;
assign n1 = i2[31];
assign n2 = ~s11_1;
assign n3 = n1 | n2;
assign n4 = ~n3;
assign n5 = 9'b000000001;
assign n6 = i1 - n5;
assign n7 = n4 ? n6 : i1;
assign n8 = {i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n9 = {i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n10 = n4 ? n8 : n9;
cf_fp_mul_p_8_23_49 s11 (s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9, s11_1);
cf_fp_mul_p_8_23_60 s12 (i1, s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9);
assign o2 = n10;
assign o1 = n7;
endmodule

module cf_fp_mul_p_8_23_34 (i1, i2, o1, o2);
input  [8:0] i1;
input  [32:0] i2;
output [8:0] o1;
output [31:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   [8:0] n5;
wire   [8:0] n6;
wire   [8:0] n7;
wire   [31:0] n8;
wire   [31:0] n9;
wire   [31:0] n10;
wire   s11_1;
wire   s12_1;
wire   s12_2;
wire   s12_3;
wire   s12_4;
wire   s12_5;
wire   s12_6;
wire   s12_7;
wire   s12_8;
wire   s12_9;
assign n1 = i2[32];
assign n2 = ~s11_1;
assign n3 = n1 | n2;
assign n4 = ~n3;
assign n5 = 9'b000000001;
assign n6 = i1 - n5;
assign n7 = n4 ? n6 : i1;
assign n8 = {i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n9 = {i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n10 = n4 ? n8 : n9;
cf_fp_mul_p_8_23_49 s11 (s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9, s11_1);
cf_fp_mul_p_8_23_60 s12 (i1, s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9);
assign o2 = n10;
assign o1 = n7;
endmodule

module cf_fp_mul_p_8_23_35 (i1, i2, o1, o2);
input  [8:0] i1;
input  [33:0] i2;
output [8:0] o1;
output [32:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   [8:0] n5;
wire   [8:0] n6;
wire   [8:0] n7;
wire   [32:0] n8;
wire   [32:0] n9;
wire   [32:0] n10;
wire   s11_1;
wire   s12_1;
wire   s12_2;
wire   s12_3;
wire   s12_4;
wire   s12_5;
wire   s12_6;
wire   s12_7;
wire   s12_8;
wire   s12_9;
assign n1 = i2[33];
assign n2 = ~s11_1;
assign n3 = n1 | n2;
assign n4 = ~n3;
assign n5 = 9'b000000001;
assign n6 = i1 - n5;
assign n7 = n4 ? n6 : i1;
assign n8 = {i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n9 = {i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n10 = n4 ? n8 : n9;
cf_fp_mul_p_8_23_49 s11 (s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9, s11_1);
cf_fp_mul_p_8_23_60 s12 (i1, s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9);
assign o2 = n10;
assign o1 = n7;
endmodule

module cf_fp_mul_p_8_23_36 (i1, i2, o1, o2);
input  [8:0] i1;
input  [34:0] i2;
output [8:0] o1;
output [33:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   [8:0] n5;
wire   [8:0] n6;
wire   [8:0] n7;
wire   [33:0] n8;
wire   [33:0] n9;
wire   [33:0] n10;
wire   s11_1;
wire   s12_1;
wire   s12_2;
wire   s12_3;
wire   s12_4;
wire   s12_5;
wire   s12_6;
wire   s12_7;
wire   s12_8;
wire   s12_9;
assign n1 = i2[34];
assign n2 = ~s11_1;
assign n3 = n1 | n2;
assign n4 = ~n3;
assign n5 = 9'b000000001;
assign n6 = i1 - n5;
assign n7 = n4 ? n6 : i1;
assign n8 = {i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n9 = {i2[34],
  i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n10 = n4 ? n8 : n9;
cf_fp_mul_p_8_23_49 s11 (s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9, s11_1);
cf_fp_mul_p_8_23_60 s12 (i1, s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9);
assign o2 = n10;
assign o1 = n7;
endmodule

module cf_fp_mul_p_8_23_37 (i1, i2, o1, o2);
input  [8:0] i1;
input  [35:0] i2;
output [8:0] o1;
output [34:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   [8:0] n5;
wire   [8:0] n6;
wire   [8:0] n7;
wire   [34:0] n8;
wire   [34:0] n9;
wire   [34:0] n10;
wire   s11_1;
wire   s12_1;
wire   s12_2;
wire   s12_3;
wire   s12_4;
wire   s12_5;
wire   s12_6;
wire   s12_7;
wire   s12_8;
wire   s12_9;
assign n1 = i2[35];
assign n2 = ~s11_1;
assign n3 = n1 | n2;
assign n4 = ~n3;
assign n5 = 9'b000000001;
assign n6 = i1 - n5;
assign n7 = n4 ? n6 : i1;
assign n8 = {i2[34],
  i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n9 = {i2[35],
  i2[34],
  i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n10 = n4 ? n8 : n9;
cf_fp_mul_p_8_23_49 s11 (s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9, s11_1);
cf_fp_mul_p_8_23_60 s12 (i1, s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7, s12_8, s12_9);
assign o2 = n10;
assign o1 = n7;
endmodule

module cf_fp_mul_p_8_23_38 (i1, i2, o1, o2);
input  [8:0] i1;
input  [36:0] i2;
output [8:0] o1;
output [35:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   [8:0] n5;
wire   [8:0] n6;
wire   [8:0] n7;
wire   [35:0] n8;
wire   [35:0] n9;
wire   [35:0] n10;
wire   s11_1;
wire   s12_1;
wire   s12_2;
wire   s12_3;
wire   s12_4;
wire   s12_5;
wire   s12_6;
wire   s12_7;
wire   s12_8;
wire   s12_9;
assign n1 = i2[36];
assign n2 = ~s11_1;
assign n3 = n1 | n2;
assign n4 = ~n3;
assign n5 = 9'b000000001;
assign n6 = i1 - n5;
assign n7 = n4 ? n6 : i1;
assign n8 = {i2[35],
  i2[34],
  i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n9 = {i2[36],
  i2[35],
  i2[34],
  i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],