cf_fp_mul_p_8_23.v

verilog浮点乘发器

  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 34'b0000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 34'b0000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_36 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_16 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_16 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [33:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [32:0] n7;
wire   [8:0] s8_1;
wire   [32:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 33'b000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 33'b000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_35 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_17 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_17 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [32:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [31:0] n7;
wire   [8:0] s8_1;
wire   [31:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 32'b00000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 32'b00000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_34 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_18 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_18 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [31:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [30:0] n7;
wire   [8:0] s8_1;
wire   [30:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 31'b0000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 31'b0000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_33 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_19 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_19 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [30:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [29:0] n7;
wire   [8:0] s8_1;
wire   [29:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 30'b000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 30'b000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_32 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_20 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_20 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [29:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [28:0] n7;
wire   [8:0] s8_1;
wire   [28:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 29'b00000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 29'b00000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_31 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_21 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_21 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [28:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [27:0] n7;
wire   [8:0] s8_1;
wire   [27:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 28'b0000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 28'b0000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_30 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_22 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_22 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [27:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [26:0] n7;
wire   s8_1;
wire   s8_2;
wire   s8_3;
wire   s8_4;
wire   s8_5;
wire   [8:0] s8_6;
wire   [23:0] s8_7;
wire   [8:0] s9_1;
wire   [26:0] s9_2;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s9_1;
initial n7 = 27'b000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 27'b000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s9_2;
cf_fp_mul_p_8_23_24 s8 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s8_1, s8_2, s8_3, s8_4, s8_5, s8_6, s8_7);
cf_fp_mul_p_8_23_23 s9 (i8, i9, s9_1, s9_2);
assign o7 = s8_7;
assign o6 = s8_6;
assign o5 = s8_5;
assign o4 = s8_4;
assign o3 = s8_3;
assign o2 = s8_2;
assign o1 = s8_1;
endmodule

module cf_fp_mul_p_8_23_23 (i1, i2, o1, o2);
input  [8:0] i1;
input  [27:0] i2;
output [8:0] o1;
output [26:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   [8:0] n5;
wire   [8:0] n6;
wire   [8:0] n7;
wire   [26:0] n8;
wire   [26:0] n9;
wire   [26:0] n10;
wire   s11_1;
wire   s12_1;
wire   s12_2;
wire   s12_3;
wire   s12_4;
wire   s12_5;
wire   s12_6;
wire   s12_7;
wire   s12_8;
wire   s12_9;
assign n1 = i2[27];
assign n2 = ~s11_1;
assign n3 = n1 | n2;
assign n4 = ~n3;
assign n5 = 9'b000000001;
assign n6 = i1 - n5;
assign n7 = n4 ? n6 : i1;
assign n8 = {i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n9 = {i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],