cf_fp_mul_p_8_23.v

verilog浮点乘发器

  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 42'b000000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 42'b000000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_44 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_8 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_8 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [41:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [40:0] n7;
wire   [8:0] s8_1;
wire   [40:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 41'b00000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 41'b00000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_43 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_9 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_9 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [40:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [39:0] n7;
wire   [8:0] s8_1;
wire   [39:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 40'b0000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 40'b0000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_42 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_10 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_10 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [39:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [38:0] n7;
wire   [8:0] s8_1;
wire   [38:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 39'b000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 39'b000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_41 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_11 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_11 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [38:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [37:0] n7;
wire   [8:0] s8_1;
wire   [37:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 38'b00000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 38'b00000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_40 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_12 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_12 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [37:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [36:0] n7;
wire   [8:0] s8_1;
wire   [36:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 37'b0000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 37'b0000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_39 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_13 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_13 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [36:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [35:0] n7;
wire   [8:0] s8_1;
wire   [35:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 36'b000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 36'b000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_38 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_14 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_14 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [35:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [34:0] n7;
wire   [8:0] s8_1;
wire   [34:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 9'b000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 9'b000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 35'b00000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 35'b00000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_8_23_37 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_8_23_15 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_8_23_15 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [8:0] i8;
input  [34:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [8:0] o6;
output [23:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [8:0] n6;
reg    [33:0] n7;
wire   [8:0] s8_1;
wire   [33:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [8:0] s9_6;
wire   [23:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)