cf_fp_mul_p_5_10.v

verilog浮点乘发器

  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_21 (i1, i2, o1, o2);
input  [5:0] i1;
input  [19:0] i2;
output [5:0] o1;
output [18:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [18:0] n7;
wire   [18:0] n8;
wire   [18:0] n9;
wire   s10_1;
assign n1 = i2[19];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_22 (i1, i2, o1, o2);
input  [5:0] i1;
input  [20:0] i2;
output [5:0] o1;
output [19:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [19:0] n7;
wire   [19:0] n8;
wire   [19:0] n9;
wire   s10_1;
assign n1 = i2[20];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_23 (i1, o1);
input  [5:0] i1;
output o1;
wire   n1;
wire   [4:0] n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
assign n1 = i1[5];
assign n2 = {i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n1 | s9_1;
assign n4 = s9_2 | s9_3;
assign n5 = s9_4 | s9_5;
assign n6 = n3 | n4;
assign n7 = n6 | n5;
assign n8 = ~n7;
cf_fp_mul_p_5_10_28 s9 (n2, s9_1, s9_2, s9_3, s9_4, s9_5);
assign o1 = n8;
endmodule

module cf_fp_mul_p_5_10_24 (i1, i2, o1, o2, o3, o4, o5, o6, o7);
input  [15:0] i1;
input  [15:0] i2;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [21:0] o7;
wire   n1;
wire   [4:0] n2;
wire   [9:0] n3;
wire   n4;
wire   [4:0] n5;
wire   [9:0] n6;
wire   n7;
wire   n8;
wire   n9;
wire   n10;
wire   n11;
wire   n12;
wire   n13;
wire   n14;
wire   n15;
wire   n16;
wire   [5:0] n17;
wire   n18;
wire   [5:0] n19;
wire   [5:0] n20;
wire   [5:0] n21;
wire   n22;
wire   [10:0] n23;
wire   n24;
wire   [10:0] n25;
wire   [21:0] n26;
wire   [5:0] n27;
wire   s28_1;
wire   s28_2;
wire   s28_3;
wire   s28_4;
wire   s28_5;
wire   s29_1;
wire   s29_2;
wire   s29_3;
wire   s29_4;
wire   s29_5;
assign n1 = i1[15];
assign n2 = {i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10]};
assign n3 = {i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n4 = i2[15];
assign n5 = {i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10]};
assign n6 = {i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n7 = s29_2 | s29_1;
assign n8 = s28_2 | s28_1;
assign n9 = n7 | n8;
assign n10 = s29_3 & s28_4;
assign n11 = s29_4 & s28_3;
assign n12 = n10 | n11;
assign n13 = s29_3 | s28_3;
assign n14 = s29_4 | s28_4;
assign n15 = n1 ^ n4;
assign n16 = 1'b0;
assign n17 = {n16, n2};
assign n18 = 1'b0;
assign n19 = {n18, n5};
assign n20 = n17 + n19;
assign n21 = n20 - n27;
assign n22 = ~s29_5;
assign n23 = {n22, n3};
assign n24 = ~s28_5;
assign n25 = {n24, n6};
assign n26 = {{11{1'b0}}, n23} * {{11{1'b0}}, n25};
assign n27 = 6'b001111;
cf_fp_mul_p_5_10_25 s28 (i2, s28_1, s28_2, s28_3, s28_4, s28_5);
cf_fp_mul_p_5_10_25 s29 (i1, s29_1, s29_2, s29_3, s29_4, s29_5);
assign o7 = n26;
assign o6 = n21;
assign o5 = n15;
assign o4 = n14;
assign o3 = n13;
assign o2 = n12;
assign o1 = n9;
endmodule

module cf_fp_mul_p_5_10_25 (i1, o1, o2, o3, o4, o5);
input  [15:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
wire   [4:0] n1;
wire   [9:0] n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
wire   n9;
wire   n10;
wire   n11;
wire   n12;
wire   [8:0] n13;
wire   n14;
wire   n15;
wire   n16;
wire   n17;
wire   n18;
wire   n19;
wire   n20;
wire   n21;
wire   n22;
wire   n23;
wire   n24;
wire   n25;
wire   s26_1;
wire   s26_2;
wire   s26_3;
wire   s26_4;
wire   s26_5;
wire   s27_1;
wire   s27_2;
wire   s27_3;
wire   s27_4;
wire   s27_5;
wire   s28_1;
wire   s28_2;
wire   s28_3;
wire   s28_4;
wire   s28_5;
wire   s28_6;
wire   s28_7;
wire   s28_8;
wire   s28_9;
wire   s29_1;
assign n1 = {i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10]};
assign n2 = {i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = s26_1 & s26_2;
assign n4 = s26_3 & s26_4;
assign n5 = n3 & n4;
assign n6 = n5 & s26_5;
assign n7 = s27_1 | s27_2;
assign n8 = s27_3 | s27_4;
assign n9 = n7 | n8;
assign n10 = n9 | s27_5;
assign n11 = ~n10;
assign n12 = n2[9];
assign n13 = {n2[8],
  n2[7],
  n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n14 = ~s29_1;
assign n15 = n2[9];
assign n16 = n6 & n15;
assign n17 = n2[9];
assign n18 = ~n17;
assign n19 = n6 & n18;
assign n20 = ~n14;
assign n21 = n19 & n20;
assign n22 = n6 & n14;
assign n23 = n11 & n14;
assign n24 = ~n14;
assign n25 = n11 & n24;
cf_fp_mul_p_5_10_28 s26 (n1, s26_1, s26_2, s26_3, s26_4, s26_5);
cf_fp_mul_p_5_10_28 s27 (n1, s27_1, s27_2, s27_3, s27_4, s27_5);
cf_fp_mul_p_5_10_27 s28 (n13, s28_1, s28_2, s28_3, s28_4, s28_5, s28_6, s28_7, s28_8, s28_9);
cf_fp_mul_p_5_10_26 s29 (n12, s28_1, s28_2, s28_3, s28_4, s28_5, s28_6, s28_7, s28_8, s28_9, s29_1);
assign o5 = n25;
assign o4 = n23;
assign o3 = n22;
assign o2 = n21;
assign o1 = n16;
endmodule

module cf_fp_mul_p_5_10_26 (i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, o1);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  i8;
input  i9;
input  i10;
output o1;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
wire   n9;
assign n1 = i1 | i2;
assign n2 = i3 | i4;
assign n3 = i5 | i6;
assign n4 = i7 | i8;
assign n5 = i9 | i10;
assign n6 = n1 | n2;
assign n7 = n3 | n4;
assign n8 = n6 | n7;
assign n9 = n8 | n5;
assign o1 = n9;
endmodule

module cf_fp_mul_p_5_10_27 (i1, o1, o2, o3, o4, o5, o6, o7, o8, o9);
input  [8:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
wire   n1;
wire   [7:0] n2;
wire   n3;
wire   [6:0] n4;
wire   n5;
wire   [5:0] n6;
wire   n7;
wire   [4:0] n8;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
assign n1 = i1[8];
assign n2 = {i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[7];
assign n4 = {n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[6];
assign n6 = {n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
assign n7 = n6[5];
assign n8 = {n6[4],
  n6[3],
  n6[2],
  n6[1],
  n6[0]};
cf_fp_mul_p_5_10_28 s9 (n8, s9_1, s9_2, s9_3, s9_4, s9_5);
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n7;
assign o3 = n5;
assign o2 = n3;
assign o1 = n1;
endmodule

module cf_fp_mul_p_5_10_28 (i1, o1, o2, o3, o4, o5);
input  [4:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
wire   n1;
wire   [3:0] n2;
wire   n3;
wire   [2:0] n4;
wire   n5;
wire   [1:0] n6;
wire   n7;
wire   n8;
wire   n9;
assign n1 = i1[4];
assign n2 = {i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[3];
assign n4 = {n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[2];
assign n6 = {n4[1],
  n4[0]};
assign n7 = n6[1];
assign n8 = n6[0];
assign n9 = n8;
assign o5 = n9;
assign o4 = n7;
assign o3 = n5;
assign o2 = n3;
assign o1 = n1;
endmodule

module cf_fp_mul_p_5_10_29 (i1, i2, i3, i4, i5, i6, i7, o1);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  [5:0] i6;
input  [10:0] i7;
output [15:0] o1;
wire   [4:0] n1;
wire   [9:0] n2;
wire   [14:0] n3;
wire   [14:0] n4;
wire   [1:0] n5;
wire   [2:0] n6;
wire   [3:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] n10;
wire   [2:0] n11;
wire   [2:0] n12;
wire   [15:0] n13;
wire   [14:0] n14;
wire   [14:0] n15;
wire   [14:0] n16;
wire   [2:0] s17_1;
wire   [14:0] s18_1;
assign n1 = {i6[4],
  i6[3],
  i6[2],
  i6[1],
  i6[0]};
assign n2 = {i7[9],
  i7[8],
  i7[7],
  i7[6],
  i7[5],
  i7[4],
  i7[3],
  i7[2],
  i7[1],
  i7[0]};
assign n3 = {n1, n2};
assign n4 = 15'b000000000000000;
assign n5 = {i3, i4};
assign n6 = {i2, n5};
assign n7 = {i1, n6};
assign n8 = 3'b000;
assign n9 = 3'b001;
assign n10 = 3'b010;
assign n11 = 3'b011;
assign n12 = 3'b100;
assign n13 = {i5, s18_1};
assign n14 = 15'b111110000000000;
assign n15 = 15'b111111111111111;
assign n16 = 15'b111110111111111;
cf_fp_mul_p_5_10_31 s17 (n7, n8, n9, n10, n11, n12, s17_1);
cf_fp_mul_p_5_10_30 s18 (n3, n4, s17_1, n14, n15, n16, s18_1);
assign o1 = n13;
endmodule

module cf_fp_mul_p_5_10_30 (i1, i2, i3, i4, i5, i6, o1);
input  [14:0] i1;
input  [14:0] i2;
input  [2:0] i3;
input  [14:0] i4;
input  [14:0] i5;
input  [14:0] i6;
output [14:0] o1;
wire   [1:0] n1;
wire   n2;
wire   [14:0] n3;
wire   [14:0] n4;
wire   n5;
wire   n6;
wire   [14:0] n7;
wire   n8;
wire   [14:0] n9;
assign n1 = {i3[2],
  i3[1]};
assign n2 = i3[0];
assign n3 = n2 ? i2 : i1;
assign n4 = n2 ? i5 : i4;
assign n5 = n1[1];
assign n6 = n1[0];
assign n7 = n6 ? n4 : n3;
assign n8 = n5;
assign n9 = n8 ? i6 : n7;
assign o1 = n9;
endmodule

module cf_fp_mul_p_5_10_31 (i1, i2, i3, i4, i5, i6, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
input  [2:0] i5;
input  [2:0] i6;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] s10_1;
assign n1 = 4'b1000;
assign n2 = i1 == n1;
assign n3 = 4'b1001;
assign n4 = i1 == n3;
assign n5 = 4'b1010;
assign n6 = i1 == n5;
assign n7 = n6 ? i6 : s10_1;
assign n8 = n4 ? i6 : n7;
assign n9 = n2 ? i6 : n8;
cf_fp_mul_p_5_10_32 s10 (i1, i2, i3, i4, i5, i6, s10_1);
assign o1 = n9;
endmodule

module cf_fp_mul_p_5_10_32 (i1, i2, i3, i4, i5, i6, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
input  [2:0] i5;
input  [2:0] i6;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] s10_1;
assign n1 = 4'b1011;
assign n2 = i1 == n1;
assign n3 = 4'b1100;
assign n4 = i1 == n3;
assign n5 = 4'b1101;
assign n6 = i1 == n5;
assign n7 = n6 ? i6 : s10_1;
assign n8 = n4 ? i6 : n7;
assign n9 = n2 ? i6 : n8;
cf_fp_mul_p_5_10_33 s10 (i1, i2, i3, i4, i5, i6, s10_1);
assign o1 = n9;
endmodule

module cf_fp_mul_p_5_10_33 (i1, i2, i3, i4, i5, i6, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
input  [2:0] i5;
input  [2:0] i6;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] s10_1;
assign n1 = 4'b1110;
assign n2 = i1 == n1;
assign n3 = 4'b1111;
assign n4 = i1 == n3;
assign n5 = 4'b0100;
assign n6 = i1 == n5;
assign n7 = n6 ? i5 : s10_1;
assign n8 = n4 ? i6 : n7;
assign n9 = n2 ? i6 : n8;
cf_fp_mul_p_5_10_34 s10 (i1, i2, i3, i4, i5, s10_1);
assign o1 = n9;
endmodule

module cf_fp_mul_p_5_10_34 (i1, i2, i3, i4, i5, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
input  [2:0] i5;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] s10_1;
assign n1 = 4'b0101;
assign n2 = i1 == n1;
assign n3 = 4'b0110;
assign n4 = i1 == n3;
assign n5 = 4'b0111;
assign n6 = i1 == n5;
assign n7 = n6 ? i5 : s10_1;
assign n8 = n4 ? i5 : n7;
assign n9 = n2 ? i5 : n8;
cf_fp_mul_p_5_10_35 s10 (i1, i2, i3, i4, s10_1);
assign o1 = n9;
endmodule

module cf_fp_mul_p_5_10_35 (i1, i2, i3, i4, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
assign n1 = 4'b0010;
assign n2 = i1 == n1;
assign n3 = 4'b0011;
assign n4 = i1 == n3;
assign n5 = 4'b0001;
assign n6 = i1 == n5;
assign n7 = n6 ? i3 : i2;
assign n8 = n4 ? i4 : n7;
assign n9 = n2 ? i4 : n8;
assign o1 = n9;
endmodule