cf_fp_mul_p_5_10.v

verilog浮点乘发器

    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 15'b000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 15'b000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_17 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_5_10_9 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_5_10_9 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [14:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [13:0] n7;
wire   [5:0] s8_1;
wire   [13:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [5:0] s9_6;
wire   [10:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 14'b00000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 14'b00000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_16 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_5_10_10 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_5_10_10 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [13:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [12:0] n7;
wire   [5:0] s8_1;
wire   [12:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [5:0] s9_6;
wire   [10:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 13'b0000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 13'b0000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_15 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_5_10_11 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_5_10_11 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [12:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [11:0] n7;
wire   [5:0] s8_1;
wire   [11:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [5:0] s9_6;
wire   [10:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 12'b000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 12'b000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_14 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_5_10_12 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_5_10_12 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [11:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [10:0] n7;
wire   [5:0] s8_1;
wire   [10:0] s8_2;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 11'b00000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 11'b00000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_13 s8 (i8, i9, s8_1, s8_2);
assign o7 = n7;
assign o6 = n6;
assign o5 = n5;
assign o4 = n4;
assign o3 = n3;
assign o2 = n2;
assign o1 = n1;
endmodule

module cf_fp_mul_p_5_10_13 (i1, i2, o1, o2);
input  [5:0] i1;
input  [11:0] i2;
output [5:0] o1;
output [10:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [10:0] n7;
wire   [10:0] n8;
wire   [10:0] n9;
wire   s10_1;
assign n1 = i2[11];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_14 (i1, i2, o1, o2);
input  [5:0] i1;
input  [12:0] i2;
output [5:0] o1;
output [11:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [11:0] n7;
wire   [11:0] n8;
wire   [11:0] n9;
wire   s10_1;
assign n1 = i2[12];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_15 (i1, i2, o1, o2);
input  [5:0] i1;
input  [13:0] i2;
output [5:0] o1;
output [12:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [12:0] n7;
wire   [12:0] n8;
wire   [12:0] n9;
wire   s10_1;
assign n1 = i2[13];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_16 (i1, i2, o1, o2);
input  [5:0] i1;
input  [14:0] i2;
output [5:0] o1;
output [13:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [13:0] n7;
wire   [13:0] n8;
wire   [13:0] n9;
wire   s10_1;
assign n1 = i2[14];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_17 (i1, i2, o1, o2);
input  [5:0] i1;
input  [15:0] i2;
output [5:0] o1;
output [14:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [14:0] n7;
wire   [14:0] n8;
wire   [14:0] n9;
wire   s10_1;
assign n1 = i2[15];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_18 (i1, i2, o1, o2);
input  [5:0] i1;
input  [16:0] i2;
output [5:0] o1;
output [15:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [15:0] n7;
wire   [15:0] n8;
wire   [15:0] n9;
wire   s10_1;
assign n1 = i2[16];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_19 (i1, i2, o1, o2);
input  [5:0] i1;
input  [17:0] i2;
output [5:0] o1;
output [16:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [16:0] n7;
wire   [16:0] n8;
wire   [16:0] n9;
wire   s10_1;
assign n1 = i2[17];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_p_5_10_23 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_p_5_10_20 (i1, i2, o1, o2);
input  [5:0] i1;
input  [18:0] i2;
output [5:0] o1;
output [17:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [5:0] n4;
wire   [5:0] n5;
wire   [5:0] n6;
wire   [17:0] n7;
wire   [17:0] n8;
wire   [17:0] n9;
wire   s10_1;
assign n1 = i2[18];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 6'b000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[18],
  i2[17],