cf_fp_mul_p_5_10.v

verilog浮点乘发器

//
//  Copyright (c) 2003 Launchbird Design Systems, Inc.
//  All rights reserved.
//  
//  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
//    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
//    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
//  
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
//  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
//  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//  
//  
//  Overview:
//  
//    Performs floating point multiply.
//  
//  Interface:
//  
//    Synchronization:
//      clock_c  : Clock input.
//  
//    Inputs:
//      a_i : Left operand.
//      b_i : Right operand.
//  
//    Outputs:
//      x_o : Result.
//  
//  Built In Parameters:
//  
//    Exponent Precision = 5
//    Mantissa Precision = 10
//    Total    Precision = 16
//    Pipeline Latency   = 14 clock cycles
//  
//  
//  
//  
//  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com
//  
//  Build Date : Fri Aug 22 09:47:04 CDT 2003
//  
//  Interface
//  
//    Build Name    : cf_fp_mul_p_5_10
//    Clock Domains : clock_c  
//    Vector Input  : a_i(16)
//    Vector Input  : b_i(16)
//    Vector Output : x_o(16)
//  
//  
//  

`timescale 1 ns / 1 ns

module cf_fp_mul_p_5_10 (clock_c, a_i, b_i, x_o);
input  clock_c;
input  [15:0] a_i;
input  [15:0] b_i;
output [15:0] x_o;
wire   [15:0] n1;
cf_fp_mul_p_5_10_1 s1 (clock_c, a_i, b_i, n1);
assign x_o = n1;
endmodule

module cf_fp_mul_p_5_10_1 (clock_c, i1, i2, o1);
input  clock_c;
input  [15:0] i1;
input  [15:0] i2;
output [15:0] o1;
wire   n1;
wire   n2;
wire   [15:0] s3_1;
assign n1 = 1'b1;
assign n2 = 1'b0;
cf_fp_mul_p_5_10_2 s3 (clock_c, n1, n2, i1, i2, s3_1);
assign o1 = s3_1;
endmodule

module cf_fp_mul_p_5_10_2 (clock_c, i1, i2, i3, i4, o1);
input  clock_c;
input  i1;
input  i2;
input  [15:0] i3;
input  [15:0] i4;
output [15:0] o1;
reg    [15:0] n1;
reg    [15:0] n2;
reg    n3;
reg    n4;
reg    n5;
reg    n6;
reg    n7;
reg    [5:0] n8;
reg    [21:0] n9;
wire   n10;
wire   [5:0] n11;
wire   [5:0] n12;
wire   [5:0] n13;
wire   [20:0] n14;
wire   [20:0] n15;
wire   [20:0] n16;
reg    n17;
reg    n18;
reg    n19;
reg    n20;
reg    n21;
reg    [5:0] n22;
reg    [20:0] n23;
reg    [15:0] n24;
wire   [15:0] s25_1;
wire   s26_1;
wire   s26_2;
wire   s26_3;
wire   s26_4;
wire   s26_5;
wire   [5:0] s26_6;
wire   [21:0] s26_7;
wire   s27_1;
wire   s27_2;
wire   s27_3;
wire   s27_4;
wire   s27_5;
wire   [5:0] s27_6;
wire   [10:0] s27_7;
initial n1 = 16'b0000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 16'b0000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= s26_1;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= s26_2;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= s26_3;
initial n6 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 1'b0;
  else if (i1 == 1'b1)
    n6 <= s26_4;
initial n7 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 1'b0;
  else if (i1 == 1'b1)
    n7 <= s26_5;
initial n8 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n8 <= 6'b000000;
  else if (i1 == 1'b1)
    n8 <= s26_6;
initial n9 = 22'b0000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n9 <= 22'b0000000000000000000000;
  else if (i1 == 1'b1)
    n9 <= s26_7;
assign n10 = n9[21];
assign n11 = 6'b000001;
assign n12 = n8 + n11;
assign n13 = n10 ? n12 : n8;
assign n14 = {n9[21],
  n9[20],
  n9[19],
  n9[18],
  n9[17],
  n9[16],
  n9[15],
  n9[14],
  n9[13],
  n9[12],
  n9[11],
  n9[10],
  n9[9],
  n9[8],
  n9[7],
  n9[6],
  n9[5],
  n9[4],
  n9[3],
  n9[2],
  n9[1]};
assign n15 = {n9[20],
  n9[19],
  n9[18],
  n9[17],
  n9[16],
  n9[15],
  n9[14],
  n9[13],
  n9[12],
  n9[11],
  n9[10],
  n9[9],
  n9[8],
  n9[7],
  n9[6],
  n9[5],
  n9[4],
  n9[3],
  n9[2],
  n9[1],
  n9[0]};
assign n16 = n10 ? n14 : n15;
initial n17 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n17 <= 1'b0;
  else if (i1 == 1'b1)
    n17 <= n3;
initial n18 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n18 <= 1'b0;
  else if (i1 == 1'b1)
    n18 <= n4;
initial n19 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n19 <= 1'b0;
  else if (i1 == 1'b1)
    n19 <= n5;
initial n20 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n20 <= 1'b0;
  else if (i1 == 1'b1)
    n20 <= n6;
initial n21 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n21 <= 1'b0;
  else if (i1 == 1'b1)
    n21 <= n7;
initial n22 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n22 <= 6'b000000;
  else if (i1 == 1'b1)
    n22 <= n13;
initial n23 = 21'b000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n23 <= 21'b000000000000000000000;
  else if (i1 == 1'b1)
    n23 <= n16;
initial n24 = 16'b0000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n24 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n24 <= s25_1;
cf_fp_mul_p_5_10_29 s25 (s27_1, s27_2, s27_3, s27_4, s27_5, s27_6, s27_7, s25_1);
cf_fp_mul_p_5_10_24 s26 (n1, n2, s26_1, s26_2, s26_3, s26_4, s26_5, s26_6, s26_7);
cf_fp_mul_p_5_10_3 s27 (clock_c, i1, i2, n17, n18, n19, n20, n21, n22, n23, s27_1, s27_2, s27_3, s27_4, s27_5, s27_6, s27_7);
assign o1 = n24;
endmodule

module cf_fp_mul_p_5_10_3 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [20:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [19:0] n7;
wire   [5:0] s8_1;
wire   [19:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [5:0] s9_6;
wire   [10:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 20'b00000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 20'b00000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_22 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_5_10_4 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_5_10_4 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [19:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [18:0] n7;
wire   [5:0] s8_1;
wire   [18:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [5:0] s9_6;
wire   [10:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 19'b0000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 19'b0000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_21 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_5_10_5 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_5_10_5 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [18:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [17:0] n7;
wire   [5:0] s8_1;
wire   [17:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [5:0] s9_6;
wire   [10:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 18'b000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 18'b000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_20 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_5_10_6 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_5_10_6 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [17:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [16:0] n7;
wire   [5:0] s8_1;
wire   [16:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [5:0] s9_6;
wire   [10:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 17'b00000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 17'b00000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_19 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_5_10_7 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_5_10_7 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [16:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [15:0] n7;
wire   [5:0] s8_1;
wire   [15:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [5:0] s9_6;
wire   [10:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 6'b000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 16'b0000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 16'b0000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_5_10_18 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_5_10_8 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_5_10_8 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [5:0] i8;
input  [15:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [5:0] o6;
output [10:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [5:0] n6;
reg    [14:0] n7;
wire   [5:0] s8_1;
wire   [14:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [5:0] s9_6;
wire   [10:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 6'b000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)