cfg_fsm.vhd

PCI的VHDL源码希望对大家有用！

--*****************************************************************************
-- FILE    : CFG_FSM.vhd
-- DATE    : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr   :
-- Entities:  CFG_FSM
-- Changes :
-- ******************************************************
-- *         Configuration Space  Entity                *
-- ******************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity CFG_FSM is
  port(
      RESET    : in  std_logic;
      CLK      : in  std_logic;
      FIRST_CYC: in  std_logic;  -- First Cycle After FRAME# falling edge
      ACC_CFG  : in  std_logic;  -- Configuration Space Access
      D_SENT   : in  std_logic;  -- Data Sent
      DRDY     : out std_logic;  -- Ready to transfer data
      OT_CFG   : out std_logic   -- CFG Space Output Buffers Control
  ); end CFG_FSM;



-- ******************************************************
-- *                     Architectures                  *
-- ******************************************************

architecture RTL of CFG_FSM is
  -- FSM State Definition
  type FSM_State_Type is (Idle,Decode, Data, Finish);
  signal currState, nextState: FSM_State_Type; -- FSM State
  -- Local Signals
begin

Sync : process (CLK, RESET) begin
    if (RESET = '1') then
      currState <= Idle;
    elsif (CLK'event and CLK = '1') then
      currState <= nextState;
    end if;
  end process;
-- Process to generate next state logic
nxtStProc: process (currState,ACC_CFG,D_SENT)
  begin
   case currState is
    when Idle   =>
        if (ACC_CFG = '1')then
          nextState <= Decode;
         else
          nextState <= Idle;
        end if;
    when Decode =>
        nextState <= Data;
    when Data =>
        nextState <= Finish;
    when Finish  =>
        if (D_SENT = '1')then
          nextState <= Idle;
         else
          nextState <= Finish;
        end if;
    when others =>
      null;
   end case;
  end process nxtStProc;
   -- Output Signal Assignment
   DRDY_Proc: process(currState)
   begin
      if (currState = Finish) then
         DRDY <= '1';
      else
         DRDY <= '0';
      end if;
   end process DRDY_Proc;
   OTCFG_Proc: process(currState)
   begin
      if (currState = Data) or (currState = Finish) then
         OT_CFG <= '0';
      else
         OT_CFG <= '1';
      end if;
   end process OTCFG_Proc;
end RTL;