user_app.vhd

PCI的VHDL源码希望对大家有用！

--*****************************************************************************
-- DESIGN  : PCI User Application Template
-- FILE    : USER_APP.vhd
-- DATE    : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr   : PCI Target user application template
-- Entities: USER_APP
-- Changes :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity USER_APP is
   port (
      APP_RST : in std_logic;
      APP_CLK : in std_logic;
      APP_ADR : in std_logic_vector(31 downto 0);
      APP_ADI : in std_logic_vector(31 downto 0);
      APP_ADO : out std_logic_vector(31 downto 0);
      APP_INTn : out std_logic;
      T_DRDY : out std_logic;
      T_ABORT : out std_logic;
      T_TERM : out std_logic;
      T_BARHIT : in std_logic_vector(5 downto 0);
      T_EBARHIT : in std_logic;
      T_BEn : in std_logic_vector(3 downto 0);
      T_CMD : in std_logic_vector(3 downto 0);
      T_RD : in std_logic;
      T_WR : in std_logic;
      T_WE : in std_logic;
      T_NEXTD : in std_logic;
      PCR_CMD : in std_logic_vector(15 downto 0);
      PCR_STAT : in std_logic_vector(15 downto 0)
      ----------------------------
      -- Add user I/O pins here --
      ----------------------------
   );
end USER_APP;

architecture Struct of USER_APP is
  --------------------------------
  --  Add User Components here  --
  --------------------------------

begin
   -- Replace this section by user design --
   T_ABORT <= '0';
   T_TERM <= '0';
   APP_INTn <='1';
   T_DRDY <= T_BARHIT(0);
   APP_ADo <= (others => '0') when T_BARHIT(0)='1' and T_RD='1' else
              (others => 'Z');
   --
end Struct;