📄 cfg_space.vhd
字号:
WE_BAR1 => WE_BAR1,
WE_BAR2 => WE_BAR2,
WE_BAR3 => WE_BAR3,
WE_BAR4 => WE_BAR4,
WE_BAR5 => WE_BAR5,
WE_EBAR => WE_EBAR,
WE_STATR => WE_STREG,
WE_CMDR => WE_CMDR,
WE_INTR => WE_INTR
); -- CFG_DECODE;
CFGROM: cfg_rom port map(
ADR =>ADR_ROM,
DATA =>DATA_ROM
);
-- Configuration ROM Tristate buffers
OEROM0: DOUT(7 downto 0) <= DATA_ROM(7 downto 0) when (OE_ROM(0)='1')
else "ZZZZZZZZ";
OEROM1: DOUT(15 downto 8) <= DATA_ROM(15 downto 8) when (OE_ROM(1)='1')
else "ZZZZZZZZ";
OEROM2: DOUT(23 downto 16) <= DATA_ROM(23 downto 16) when (OE_ROM(2)='1')
else "ZZZZZZZZ";
OEROM3: DOUT(31 downto 24) <= DATA_ROM(31 downto 24) when (OE_ROM(3)='1')
else "ZZZZZZZZ";
--
-- Command Register : ADDR = 04h
--
U2: CFG_CMDREG port map(
RESET => RESET,
CLK => CLK,
DIN => DIN(15 downto 0),
DOUT => DOUT(15 downto 0),
BEn => BEn,
WE => WE_CMDR,
OE => OE_CMDR,
PCR_CMD => PCR_CMD,
IO_EN => IO_EN, -- I/O Space Decoding Enabled
MEM_EN => MEM_EN, -- Memory Space Decoding Enabled
SPEC_CYC => SPEC_CYC, -- Special Cycles Monitoring Enabled
PERR_EN => PERR_EN, -- Parity Error Response
STEPPING_EN => STEPPING_EN , -- Stepping Control
SERR_EN => SERR_EN -- SERR# Enable
); -- CFG_CMDREG;
--
-- Status Register : ADDR = 06h
--
U3: CFG_STREG port map(
RESET => RESET,
CLK => CLK,
DIN => DIN(31 downto 16),
DOUT => DOUT(31 downto 16),
BEn => BEn,
WE => WE_STREG ,
OE => OE_STREG ,
SET_MDPERR => SET_MDPERR , -- Set Master Data Parity Error Bit(
8)
SIG_TABORT => SIG_TABORT , -- Set Signaled Target Abort Bit
(11)
RCV_TABORT => RCV_TABORT , -- Set Received Target Abort Bit
(12)
RCV_MABORT => RCV_MABORT , -- Set Received Master Abort Bit
(13)
SIG_SERR => SIG_SERR , -- Set Signaled System Error Bit
(14)
DET_PERR => DET_PERR, -- Set Detected Parity Error Bit
(15)
PCR_STAT => PCR_STAT
); -- end CFG_STREG;
--
-- Interrupt Line Register : ADDR = 3Ch
--
U6: CFG_INTREG port map(
RESET => RESET,
CLK => CLK,
DIN => DIN(7 downto 0),
DOUT => DOUT(7 downto 0),
WE => WE_INTR,
OE => OE_INTR
); -- end CFG_INTREG;
--******************************
--* Adaptor Space Hit Decoding *
--******************************
EQ1: CARD_HITi <= ACC_CFG or BAR0_HIT or BAR1_HIT or BAR2_HIT or BAR3_HIT
or BAR4_HIT or BAR5_HIT or EBAR_HIT;
CARD_HIT <= CARD_HITi;
-- Target Active S-R Register
TAD: process (CLK,RESET)
begin
if RESET='1' then --synchronous RESET active High
TARGET_ACT <= '0';
elsif CLK'event and CLK='1' then --CLK rising edge
if ACC_END = '1' then
TARGET_ACT <= '0';
elsif CARD_HITi ='1' then
TARGET_ACT <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Base Address Register 0 : ADDR = 10h
-------------------------------------------------------------------------------
BAR0I: if BAR0_MAP(0) = '1' generate
AS1B0I: BAR0_ACC <= ACC_IO ;
end generate;
--
BAR0M: if BAR0_MAP(0) = '0' generate
AS1B0M: BAR0_ACC <= ACC_MEM ;
end generate;
--
BAR0: BAR_REG
generic map(
BAR_NO => 0)
port map(
RESET => RESET,
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
BEn => BEn,
RD => OE_BAR0,
WR => WE_BAR0,
ACC_SPACE=> BAR0_ACC,
FIRST_CYC=> FIRST_CYC,
HIT => BAR0_HIT,
SIZE => BAR0_SIZE
);
-------------------------------------------------------------------------------
-- Base Address Register 1 : ADDR = 14h
-------------------------------------------------------------------------------
BAR1I: if BAR1_MAP(0) = '1' generate
AS1B1I: BAR1_ACC <= ACC_IO ;
end generate;
--
BAR1M: if BAR1_MAP(0) = '0' generate
AS1B1M: BAR1_ACC <= ACC_MEM ;
end generate;
--
BAR1: BAR_REG
generic map(BAR_NO => 1)
port map(
RESET => RESET,
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
BEn => BEn,
RD => OE_BAR1,
WR => WE_BAR1,
ACC_SPACE => BAR1_ACC,
FIRST_CYC => FIRST_CYC,
HIT => BAR1_HIT,
SIZE => BAR1_SIZE);
-------------------------------------------------------------------------------
-- Base Address Register 2 : ADDR = 18h
-------------------------------------------------------------------------------
BAR2I: if BAR2_MAP(0) = '1' generate
AS1B2I: BAR2_ACC <= ACC_IO ;
end generate;
--
BAR2M: if BAR2_MAP(0) = '0' generate
AS1B2M: BAR2_ACC <= ACC_MEM ;
end generate;
--
BAR2: BAR_REG
generic map(BAR_NO => 2)
port map(
RESET => RESET,
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
BEn => BEn,
RD => OE_BAR2,
WR => WE_BAR2,
ACC_SPACE=> BAR2_ACC,
FIRST_CYC=> FIRST_CYC,
HIT => BAR2_HIT,
SIZE => BAR2_SIZE);
-------------------------------------------------------------------------------
-- Base Address Register 3 : ADDR = 1Ch
-------------------------------------------------------------------------------
BAR3I: if BAR3_MAP(0) = '1' generate
AS1B2I: BAR3_ACC <= ACC_IO ;
end generate;
--
BAR3M: if BAR3_MAP(0) = '0' generate
AS1B2M: BAR3_ACC <= ACC_MEM ;
end generate;
--
BAR3:BAR_REG
generic map(BAR_NO => 3)
port map(
RESET => RESET,
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
BEn => BEn,
RD => OE_BAR3,
WR => WE_BAR3,
ACC_SPACE=> BAR3_ACC,
FIRST_CYC=> FIRST_CYC,
HIT => BAR3_HIT,
SIZE => BAR3_SIZE);
-------------------------------------------------------------------------------
-- Base Address Register 4 : ADDR = 20h
-------------------------------------------------------------------------------
BAR4I: if BAR4_MAP(0) = '1' generate
AS1B2I: BAR4_ACC <= ACC_IO ;
end generate;
--
BAR4M: if BAR4_MAP(0) = '0' generate
AS1B2M: BAR4_ACC <= ACC_MEM ;
end generate;
--
BAR4:BAR_REG
generic map(BAR_NO => 4)
port map(
RESET => RESET,
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
BEn => BEn,
RD => OE_BAR4,
WR => WE_BAR4,
ACC_SPACE=> BAR4_ACC,
FIRST_CYC=> FIRST_CYC,
HIT => BAR4_HIT,
SIZE => BAR4_SIZE);
-------------------------------------------------------------------------------
-- Base Address Register 5 : ADDR = 24h
-------------------------------------------------------------------------------
BAR5I: if BAR5_MAP(0) = '1' generate
AS1B2I: BAR5_ACC <= ACC_IO ;
end generate;
--
BAR5M: if BAR5_MAP(0) = '0' generate
AS1B2M: BAR5_ACC <= ACC_MEM ;
end generate;
--
BAR5: BAR_REG
generic map(BAR_NO => 5)
port map(
RESET => RESET,
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
BEn => BEn,
RD => OE_BAR5,
WR => WE_BAR5,
ACC_SPACE=> BAR5_ACC,
FIRST_CYC=> FIRST_CYC,
HIT => BAR5_HIT,
SIZE => BAR5_SIZE);
-------------------------------------------------------------------------------
-- Expansion ROM Base Address Register : ADDR = 30h
-------------------------------------------------------------------------------
EBR: EBAR port map(
RESET => RESET,
CLK => CLK,
DIN => DIN,
DOUT => DOUT,
BEn => BEn,
RD => OE_EBAR,
WR => WE_EBAR,
ACC_SPACE=> ACC_MEM, -- Memory Space decoding only
FIRST_CYC=> FIRST_CYC,
HIT => EBAR_HIT,
SIZE => EBAR_SIZE);
-------------------------------------------------------------------------------
--
-- Card BAR's HIT register
--
HITREG: process (CLK,RESET)
begin
if RESET = '1' then
BAR_HIT <= "000000";
ROM_HIT <= '0';
elsif (CLK'event and CLK='1')then
if ACC_END ='1' then
BAR_HIT <= "000000";
ROM_HIT <= '0';
elsif FIRST_CYC ='1' then
BAR_HIT(0)<= BAR0_HIT;
BAR_HIT(1)<= BAR1_HIT;
BAR_HIT(2)<= BAR2_HIT;
BAR_HIT(3)<= BAR3_HIT;
BAR_HIT(4)<= BAR4_HIT;
BAR_HIT(5)<= BAR5_HIT;
ROM_HIT <= EBAR_HIT;
end if;
end if;
end process HITREG;
--
-- Configuration space access control FSM
--
C1: CFG_FSM port map(
RESET => RESET,
CLK => CLK,
FIRST_CYC=> FIRST_CYC,
ACC_CFG => ACC_CFG, -- Configuration Space Access
D_SENT => D_SENT, -- Data Sent
DRDY => LDRDY, -- Ready to transfer data
OT_CFG => OT_CFG -- CFG Space Output Buffers Control
);
-- DRDY signal assignment
DRDY <= LDRDY;
end Struct;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -