cfg_space.vhd

PCI的VHDL源码希望对大家有用！

--*****************************************************************************
-- FILE    : CFG_SPACE.vhd
-- DATE    : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
-- Descr   : PCI Configuration Space Entity
-- Entities: CFG_SPACE
-- Changes :
--           4.8.1999 - added visibility of Command and Status register bits
--                      at the backend interface (PCR_CMD, PCR_STAT)
--
-- ******************************************************
-- *         PCI Configuration Space Entity             *
-- ******************************************************
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
entity CFG_SPACE is
   port(
      RESET       : in  std_logic;
      CLK         : in  std_logic;
      -- Data Bus
      DIN         : in  std_logic_vector(31 downto 0);-- Data IN
      DOUT        : out std_logic_vector(31 downto 0);-- Data OUT
      -- Control Signals
      ADR         : in  std_logic_vector(7 downto 2);	-- Register Address
      BEn         : in  std_logic_vector(3 downto 0);	-- Byte Enables
      CMD_CFGRD   : in  std_logic; -- PCI Command Config. Read
      CMD_CFGWR   : in  std_logic; -- PCI Command Config. Write
      ACC_START   : in  std_logic; -- Start of Device Access
      ACC_END     : in  std_logic; -- End of Device Access
      D_SENT      : in  std_logic; -- Data Sent
      FIRST_CYC   : in  std_logic; -- First Cycle After FRAME# falling edge
      ACC_CFG     : in  std_logic; -- Configuration Space Access
      ACC_IO      : in  std_logic; -- I/O Space Access
      ACC_MEM     : in  std_logic; -- Memory Space Access
      -- Device Status Register
      SET_MDPERR  : in  std_logic; -- Set Master Data Parity Error Bit( 8)
      SIG_TABORT  : in  std_logic; -- Set Signaled Target Abort Bit   (11)
      RCV_TABORT  : in  std_logic; -- Set Received Target Abort Bit   (12)
      RCV_MABORT  : in  std_logic; -- Set Received Master Abort Bit   (13)
      SIG_SERR    : in  std_logic; -- Set Signaled System Error Bit   (14)
      DET_PERR    : in  std_logic; -- Set Detected Parity Error Bit   (15)
      --
      DRDY        : out std_logic; -- Ready to transfer data
      CARD_HIT    : out std_logic; -- Card was decoded as target
      TARGET_ACT  : out std_logic; -- Target is active
      BAR_HIT     : out std_logic_vector(5 downto 0); -- BAR Hit signal
      ROM_HIT     : out std_logic; -- Expansion ROM BAR Hit
      -- Device Control Register
      PCR_CMD     : out std_logic_vector(15 downto 0); -- Command Register 
Contens
      PCR_STAT    : out std_logic_vector(15 downto 0); -- Status Register 
Contens
      IO_EN       : out std_logic; -- I/O Space Decoding Enabled
      MEM_EN      : out std_logic; -- Memory Space Decoding Enabled
      SPEC_CYC    : out std_logic; -- Special Cycles Monitoring Enabled
      PERR_EN     : out std_logic; -- Parity Error Response
      STEPPING_EN : out std_logic; -- Stepping Control
      SERR_EN     : out std_logic -- SERR# Enable
   );
end CFG_SPACE;

-- ******************************************************
-- *                     Architecture                   *
-- ******************************************************
architecture Struct of CFG_SPACE is
   -- Component declaration of the "CFG_DECODE(RTL)" unit
   -- File name contains "CFG_DECODE" entity: .\CFG_DECODE.vhd
   component CFG_DECODE
   port(
      ADR : in std_logic_vector(7 downto 2);
      BEn : in std_logic_vector(3 downto 0);
      DRDY : in std_logic;
      CMD_CFGRD : in std_logic;
      CMD_CFGWR : in std_logic;
      BAR0_SIZE : in std_logic;
      BAR1_SIZE : in std_logic;
      BAR2_SIZE : in std_logic;
      BAR3_SIZE : in std_logic;
      BAR4_SIZE : in std_logic;
      BAR5_SIZE : in std_logic;
      EBAR_SIZE : in std_logic;
      OE_ROM : out std_logic_vector(3 downto 0);
      ADR_ROM : out std_logic_vector(3 downto 0);
      OE_BAR0 : out std_logic;
      OE_BAR1 : out std_logic;
      OE_BAR2 : out std_logic;
      OE_BAR3 : out std_logic;
      OE_BAR4 : out std_logic;
      OE_BAR5 : out std_logic;
      OE_EBAR : out std_logic;
      OE_STATR : out std_logic;
      OE_CMDR : out std_logic;
      OE_INTR : out std_logic;
      WE_BAR0 : out std_logic;
      WE_BAR1 : out std_logic;
      WE_BAR2 : out std_logic;
      WE_BAR3 : out std_logic;
      WE_BAR4 : out std_logic;
      WE_BAR5 : out std_logic;
      WE_EBAR : out std_logic;
      WE_STATR : out std_logic;
      WE_CMDR : out std_logic;
      WE_INTR : out std_logic);
   end component;
   --
   component CFG_FSM is
      port(
         RESET       : in  std_logic;
         CLK         : in  std_logic;
         FIRST_CYC   : in  std_logic; -- First Cycle After FRAME# falling 
edge
         ACC_CFG     : in  std_logic; -- Configuration Space Access
         D_SENT      : in  std_logic; -- Data Sent
         DRDY        : out std_logic; -- Ready to transfer data
         OT_CFG      : out std_logic  -- CFG Space Output Buffers Control
   ); end component CFG_FSM;
   -- Component declaration of the CFG_CMDREG unit
   -- File name contains CFG_CMDREG entity: .\CFG_REGS.vhd
   component CFG_CMDREG is
      port(
         RESET       : in  std_logic;
         CLK         : in  std_logic;
         DIN         : in  std_logic_vector(15 downto 0); -- Data IN
         DOUT        : out std_logic_vector(15 downto 0); -- Data OUT
         BEn         : in std_logic_vector(3 downto 0);
         WE          : in  std_logic;
         OE          : in  std_logic;
         PCR_CMD     : out std_logic_vector(15 downto 0);
         IO_EN       : out std_logic;        -- I/O Space Decoding Enabled
         MEM_EN      : out std_logic;        -- Memory Space Decoding 
Enabled
         SPEC_CYC    : out std_logic;        -- Special Cycles Monitoring 
Enabled
         PERR_EN     : out std_logic;        -- Parity Error Response
         STEPPING_EN : out std_logic;        -- Stepping Control
         SERR_EN     : out std_logic         -- SERR# Enable
   ); end component CFG_CMDREG;
   -- Component declaration of the CFG_STREG unit
   -- File name contains CFG_STREG entity: .\CFG_REGS.vhd
   component CFG_STREG is
   port(
      RESET       : in  std_logic;
      CLK         : in  std_logic;
      DIN         : in  std_logic_vector(15 downto 0);-- Data IN
      DOUT        : out std_logic_vector(15 downto 0);-- Data OUT
      BEn         : in std_logic_vector(3 downto 0);
      WE          : in  std_logic;
      OE          : in  std_logic;
      SET_MDPERR  : in  std_logic;              -- Set Master Data Parity 
Error Bit( 8)
      SIG_TABORT  : in  std_logic;              -- Set Signaled Target Abort 
Bit   (11)
      RCV_TABORT  : in  std_logic;              -- Set Received Target Abort 
Bit   (12)
      RCV_MABORT  : in  std_logic;              -- Set Received Master Abort 
Bit   (13)
      SIG_SERR	   : in  std_logic;              -- Set Signaled System Error 
Bit   (14)
      DET_PERR	   : in  std_logic;              -- Set Detected Parity Error 
Bit   (15)
      PCR_STAT    : out std_logic_vector(15 downto 0) -- Status Register 
Contens
   );end component CFG_STREG;
   -- Component declaration of the CFG_INTREG unit
   -- File name contains CFG_INTREG entity: .\CFG_REGS.vhd
   component CFG_INTREG is
      port(
         RESET    : in  std_logic;
         CLK      : in  std_logic;
         DIN      : in  std_logic_vector(7 downto 0);	-- Data IN
         DOUT     : out std_logic_vector(7 downto 0);	-- Data OUT
         WE       : in  std_logic;
         OE       : in  std_logic
   ); end component CFG_INTREG;
   -- Component declaration of the CFG_ROM unit
   -- File name contains CFG_ROM entity: .\CFG_ROM.vhd
   component cfg_rom IS
      port(
         ADR : in  std_logic_vector(3 DOWNTO 0);
         DATA: out std_logic_vector(31 DOWNTO 0)
   ); end component cfg_rom;
   -- Component declaration of the BAR_REG unit
   -- File name contains BAR_REG entity: .\CFG_REGS.VHD
   component BAR_REG
      generic(
         BAR_NO : INTEGER );
      port(
         RESET : in std_logic;
         CLK : in std_logic;
         DIN : in std_logic_vector(31 downto 0);
         DOUT : out std_logic_vector(31 downto 0);
         BEn : in std_logic_vector(3 downto 0);
         RD : in std_logic;
         WR : in std_logic;
         ACC_SPACE : in std_logic;
         FIRST_CYC : in std_logic;
         HIT : out std_logic;
         SIZE : out std_logic);
      end component;
   -- Component declaration of the EBAR unit
   -- File name contains EBAR entity: .\CFG_REGS.vhd
   component EBAR is
      port(
         RESET       : in  std_logic;
         CLK         : in  std_logic;
         DIN         : in  std_logic_vector(31 downto 0);
         DOUT        : out std_logic_vector(31 downto 0);
         BEn         : in  std_logic_vector(3 downto 0);
         RD          : in  std_logic;
         WR          : in  std_logic;
         ACC_SPACE   : in  std_logic;
         FIRST_CYC   : in  std_logic;
         HIT         : out std_logic;
         SIZE        : out std_logic
   );end component EBAR;

  -- **********************************
  -- *      internal signals          *
  -- **********************************
   signal OE_ROM  : std_logic_vector(3 downto 0);
   signal ADR_ROM : std_logic_vector(3 downto 0);
   signal DATA_ROM: std_logic_vector(31 downto 0);
   signal OE_EBAR : std_logic;
   signal OE_STREG: std_logic;
   signal OE_CMDR : std_logic;
   signal OE_CLIR : std_logic;
   signal OE_LATR : std_logic;
   signal OE_INTR : std_logic;
   signal WE_EBAR : std_logic;
   signal WE_STREG: std_logic;
   signal WE_CMDR : std_logic;
   signal WE_CLIR : std_logic;
   signal WE_LATR : std_logic;
   signal WE_INTR : std_logic;
   --
   signal IO_ENi	: std_logic;
   signal MEM_ENi  : std_logic;-- Memory Space Decoding Enabled
   -- BAR0 Signals
   signal OE_BAR0 : std_logic;
   signal WE_BAR0 : std_logic;
   signal BAR0_ACC : std_logic;--
   signal BAR0_HIT, BAR0_SIZE  : std_logic;
   -- BAR1 Signals
   signal OE_BAR1 : std_logic;
   signal WE_BAR1 : std_logic;
   signal BAR1_PRSNT:boolean;
   signal BAR1_ACC : std_logic;--
   signal BAR1_WE, BAR1_OE : std_logic;
   signal B1_Hit, B1_Size : std_logic;
   signal BAR1_HIT, BAR1_SIZE  : std_logic;
   -- BAR2 Signals
   signal OE_BAR2 : std_logic;
   signal WE_BAR2 : std_logic;
   signal BAR2_PRSNT:boolean;
   signal BAR2_ACC : std_logic;--
   signal BAR2_WE, BAR2_OE : std_logic;
   signal B2_Hit, B2_Size : std_logic;
   signal BAR2_HIT, BAR2_SIZE  : std_logic;
   -- BAR3 Signals
   signal OE_BAR3 : std_logic;
   signal WE_BAR3 : std_logic;
   signal BAR3_ACC : std_logic;--
   signal BAR3_HIT, BAR3_SIZE  : std_logic;
   -- BAR4 Signals
   signal OE_BAR4 : std_logic;
   signal WE_BAR4 : std_logic;
   signal BAR4_ACC : std_logic;--
   signal BAR4_HIT, BAR4_SIZE  : std_logic;
   -- BAR5 Signals
   signal OE_BAR5 : std_logic;
   signal WE_BAR5 : std_logic;
   signal BAR5_ACC : std_logic;--
   signal BAR5_HIT, BAR5_SIZE  : std_logic;
   -- EBAR Signals
   signal EBAR_HIT, EBAR_SIZE  : std_logic;
   signal LDRDY :  std_logic;
  --
   signal CARD_HITi : std_logic;
   signal OT_CFG : std_logic;
begin
    U1: CFG_DECODE port map(
      ADR         => ADR(7 downto 2),
      BEn         => BEn,
      DRDY        => LDRDY,
      CMD_CFGRD   => CMD_CFGRD, -- PCI Command Config. Read
      CMD_CFGWR   => CMD_CFGWR, -- PCI Command Config. Write
      BAR0_SIZE   => BAR0_SIZE,
      BAR1_SIZE   => BAR1_SIZE,
      BAR2_SIZE   => BAR2_SIZE,
      BAR3_SIZE   => BAR3_SIZE,
      BAR4_SIZE   => BAR4_SIZE,
      BAR5_SIZE   => BAR5_SIZE,
      EBAR_SIZE   => EBAR_SIZE,
      OE_ROM      => OE_ROM,
      ADR_ROM     => ADR_ROM,
      OE_BAR0     => OE_BAR0,
      OE_BAR1     => OE_BAR1,
      OE_BAR2     => OE_BAR2,
      OE_BAR3     => OE_BAR3,
      OE_BAR4     => OE_BAR4,
      OE_BAR5     => OE_BAR5,
      OE_EBAR     => OE_EBAR,
      OE_STATR    => OE_STREG,
      OE_CMDR     => OE_CMDR,
      OE_INTR     => OE_INTR,
      WE_BAR0     => WE_BAR0,