📄 oc8051_decoder.v
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wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_CY;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_JMP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_BIT;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_JNB : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_BIT;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_JNC : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_CY;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_JNZ : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = !eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_AZ;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_JZ : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = eq;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_AZ;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_MOVC_DP :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DP;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_DES;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_MOVC_PC :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = 2'bxx;
src_sel3 = `OC8051_AS3_DP;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_Y;
rom_addr_sel = `OC8051_RAS_DES;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_SJMP : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_ALU;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
default begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
endcase
2'b11:
casex (op)
`OC8051_CJNE_R : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_OP2;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CJNE_I : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_OP2;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CJNE_D : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_OP2;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_CJNE_C : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_OP2;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_DJNZ_R : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_OP2;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP2;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_DJNZ_D : begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = `OC8051_ASS_OP2;
alu_op = `OC8051_ALU_PCS;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_OP3;
src_sel3 = `OC8051_AS3_PC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_RET : begin
ram_rd_sel = `OC8051_RRS_SP;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_SP;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
`OC8051_RETI : begin
ram_rd_sel = `OC8051_RRS_SP;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_RAM;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_SP;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
default begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_DC;
src_sel1 = `OC8051_ASS_DC;
src_sel2 = `OC8051_ASS_DC;
alu_op = `OC8051_ALU_NOP;
wr = 1'b0;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_N;
pc_sel = `OC8051_PIS_DC;
imm_sel = `OC8051_IDS_DC;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
wad2 = `OC8051_WAD_N;
rom_addr_sel = `OC8051_RAS_PC;
ext_addr_sel = `OC8051_EAS_DC;
end
endcase
default: begin
casex (op_in)
`OC8051_ACALL :begin
ram_rd_sel = `OC8051_RRS_DC;
ram_wr_sel = `OC8051_RWS_SP;
src_sel1 = `OC8051_ASS_IMM;
src_sel2 = 2'bxx;
alu_op = `OC8051_ALU_NOP;
imm_sel = `OC8051_IDS_PCL;
wr = 1'b1;
psw_set = `OC8051_PS_NOT;
cy_sel = `OC8051_CY_0;
pc_wr = `OC8051_PCW_Y;
pc_sel = `OC8051_PIS_I11;
src_sel3 = `OC8051_AS3_DC;
comp_sel = `OC8051_CSS_DC;
bit_addr = 1'b0;
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