📄 oc8051_top.srr
字号:
oc8051_top_1.oc8051_alu1.G_40 LUT2 I1 In 16.777
oc8051_top_1.oc8051_alu1.G_40 LUT2 O Out 1.690 18.467
N_174 Net 3
oc8051_top_1.oc8051_alu1.sub8_0_axbxc1 LUT2 I1 In 18.467
oc8051_top_1.oc8051_alu1.sub8_0_axbxc1 LUT2 O Out 1.546 20.013
sub8_0[1] Net 2
oc8051_top_1.oc8051_alu1.sub8_2_axb_1 LUT2 I0 In 20.013
oc8051_top_1.oc8051_alu1.sub8_2_axb_1 LUT2 O Out 1.546 21.559
sub8_2_axb_1 Net 2
oc8051_top_1.oc8051_alu1.sub8_2_cry_1 MUXCY_L S In 21.559
oc8051_top_1.oc8051_alu1.sub8_2_cry_1 MUXCY_L LO Out 0.745 22.304
sub8_2_cry_1 Net 2
oc8051_top_1.oc8051_alu1.sub8_2_cry_2 MUXCY_L CI In 22.304
oc8051_top_1.oc8051_alu1.sub8_2_cry_2 MUXCY_L LO Out -0.141 22.163
sub8_2_cry_2 Net 1
oc8051_top_1.oc8051_alu1.sub8_2_s_3 XORCY CI In 22.163
oc8051_top_1.oc8051_alu1.sub8_2_s_3 XORCY O Out 0.785 22.948
sub8[3] Net 3
oc8051_top_1.oc8051_alu1.des1_6_am[7] LUT2 I1 In 22.948
oc8051_top_1.oc8051_alu1.des1_6_am[7] LUT2 O Out 1.305 24.253
des1_6_am[7] Net 1
oc8051_top_1.oc8051_alu1.des1_6[7] MUXF5 I0 In 24.253
oc8051_top_1.oc8051_alu1.des1_6[7] MUXF5 O Out 1.171 25.423
N_108 Net 1
oc8051_top_1.oc8051_alu1.des1_10_0[7] LUT3 I1 In 25.423
oc8051_top_1.oc8051_alu1.des1_10_0[7] LUT3 O Out 1.305 26.728
N_143 Net 1
oc8051_top_1.oc8051_alu1.des1_bm[7] LUT3 I2 In 26.728
oc8051_top_1.oc8051_alu1.des1_bm[7] LUT3 O Out 1.305 28.033
des1_bm[7] Net 1
oc8051_top_1.oc8051_alu1.des1[7] MUXF5 I1 In 28.033
oc8051_top_1.oc8051_alu1.des1[7] MUXF5 O Out 0.775 28.808
des1[7] Net 20
oc8051_top_1.oc8051_indi_addr1.G_207 LUT3 I0 In 28.808
oc8051_top_1.oc8051_indi_addr1.G_207 LUT3 O Out 0.555 29.363
ri[7] Net 3
oc8051_top_1.oc8051_ext_addr_sel1.G_100 LUT3 I1 In 29.363
oc8051_top_1.oc8051_ext_addr_sel1.G_100 LUT3 O Out 1.546 30.910
buff_5[7] Net 2
oc8051_top_1.oc8051_ext_addr_sel1.G_101 LUT3 I0 In 30.910
oc8051_top_1.oc8051_ext_addr_sel1.G_101 LUT3 O Out 0.555 31.465
ext_addr_c[7] Net 1
ext_addr_obuf[7] OBUF I In 31.465
ext_addr_obuf[7] OBUF O Out 4.331 35.796
ext_addr[7] Net 1
ext_addr[15:0] Port ext_addr[7] Out 35.796
================================================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with worst slack
********************************
Arrival
Instance Type Pin Net Time Slack
-----------------------------------------------------------
rst Port rst rst 0.000 177.012
int1 Port int1 int1 0.000 193.158
int2 Port int2 int2 0.000 193.158
int3 Port int3 int3 0.000 193.532
===========================================================
Ending Points with worst slack
******************************
Required
Instance Type Pin Net Time Slack
---------------------------------------------------------------------------------------------------------------------
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[0] rd_addr_m[0] 198.800 177.012
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[1] rd_addr_m[1] 198.800 177.012
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[2] rd_addr_m[2] 198.800 177.012
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[3] rd_addr_m[3] 198.800 178.702
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[4] rd_addr_m[4] 198.800 178.702
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[5] rd_addr_m[5] 198.800 178.702
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[6] rd_addr_m[6] 198.800 178.702
oc8051_top_1.oc8051_sp1.data_out[7] FDC D data_out_s[7] 199.671 178.904
oc8051_top_1.oc8051_sp1.data_out[6] FDC D data_out_s[6] 199.671 179.004
oc8051_top_1.oc8051_sp1.data_out[5] FDC D data_out_s[5] 199.671 179.104
=====================================================================================================================
Worst Paths Information
***********************
Path information for path number 1:
- Setup time: 1.200
= Required time: 198.800
- Propagation time: 21.788
= Slack (non-critical) : 177.012
Starting point: rst / rst
Ending point: oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 / ADDRA[0]
The start point is clocked by clk [rising]
The end point is clocked by clk [rising] on pin CLKA
Instance / Net Pin Pin Arrival Fan
Name Type Name Dir Delay Time Out
--------------------------------------------------------------------------------------------------------------------------
rst Port rst In 0.000 0.000
rst Net 1
rst_ibuf IBUF I In 0.000
rst_ibuf IBUF O Out 1.993 1.993
rst_c Net 15
oc8051_top_1.oc8051_decoder1.G_2124 LUT3 I0 In 1.993
oc8051_top_1.oc8051_decoder1.G_2124 LUT3 O Out 2.305 4.298
N_3421 Net 12
oc8051_top_1.oc8051_decoder1.G_2125 LUT2 I1 In 4.298
oc8051_top_1.oc8051_decoder1.G_2125 LUT2 O Out 3.489 7.786
N_3422 Net 25
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_and2_6[1] LUT4 I2 In 7.786
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_and2_6[1] LUT4 O Out 1.546 9.332
N_3285 Net 2
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_202 LUT4 I0 In 9.332
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_202 LUT4 O Out 1.305 10.637
ram_rd_sel_0_0_0_1_202 Net 1
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_203 LUT4 I0 In 10.637
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_203 LUT4 O Out 1.305 11.942
ram_rd_sel_0_0_0_1_203 Net 1
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_205 LUT4 I0 In 11.942
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_205 LUT4 O Out 1.305 13.247
ram_rd_sel_0_0_0_1_205 Net 1
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_207 LUT4 I1 In 13.247
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_207 LUT4 O Out 1.305 14.552
ram_rd_sel_0_0_0_1_207 Net 1
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_208 LUT4 I0 In 14.552
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0_1_208 LUT4 O Out 1.305 15.857
ram_rd_sel_0_0_0_1_208 Net 1
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0[1] LUT4 I1 In 15.857
oc8051_top_1.oc8051_decoder1.ram_rd_sel_0_0_0[1] LUT4 O Out 0.555 16.412
ram_rd_sel[1] Net 12
oc8051_top_1.oc8051_ram_rd_sel1.out_3_am[7] LUT3 I0 In 16.412
oc8051_top_1.oc8051_ram_rd_sel1.out_3_am[7] LUT3 O Out 1.305 17.717
out_3_am[7] Net 1
oc8051_top_1.oc8051_ram_rd_sel1.out_3[7] MUXF5 I0 In 17.717
oc8051_top_1.oc8051_ram_rd_sel1.out_3[7] MUXF5 O Out 1.076 18.793
rd_addr[7] Net 7
oc8051_top_1.oc8051_ram_top1.rd_addr_m_sn.G_3 LUT2 I1 In 18.793
oc8051_top_1.oc8051_ram_top1.rd_addr_m_sn.G_3 LUT2 O Out 1.690 20.483
N_2_0 Net 3
oc8051_top_1.oc8051_ram_top1.rd_addr_m[0] LUT4 I0 In 20.483
oc8051_top_1.oc8051_ram_top1.rd_addr_m[0] LUT4 O Out 1.305 21.788
rd_addr_m[0] Net 1
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[0] In 21.788
==========================================================================================================================
##### END TIMING REPORT #####
---------------------------------------
Resource Usage Report for oc8051_fpga_top
Mapping to part: xcv800hq240-6
Cell usage:
FDS 4 uses
FDR 32 uses
FD 44 uses
FDPE 32 uses
MUXF5 157 uses
MUXF6 15 uses
FDC 97 uses
FDCE 96 uses
MUXCY_L 67 uses
XORCY 69 uses
FDP 3 uses
VCC 3 uses
GND 4 uses
RAMB4_S8_S8 1 use
MULT_AND 6 uses
MUXCY 3 uses
FDE 12 uses
FDSE 2 uses
FDRE 9 uses
I/O primitives:
IBUF 4 uses
OBUF 75 uses
BUFGP 1 use
I/O Register bits: 0
Register bits not including I/Os: 331 (1%)
RAM/ROM usage summary
32x1 ROMs (ROM32X1): 32
Block Rams : 1 of 28 (3%)
Global buffer usage summary
BUFGs + BUFGPs: 1 of 4 (25%)
Mapping Summary:
Total LUTs: 1300 (6%)
Mapper successful!
Process took 129.02 seconds realtime, 129.07 seconds cputime
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