📄 oc8051_top.srr
字号:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
----------------------------------------------------------------------------
clk NA NA NA NA NA
int1 System (rising) NA 0.000 193.158 193.158
int2 System (rising) NA 0.000 193.158 193.158
int3 System (rising) NA 0.000 193.532 193.532
rst System (rising) NA 0.000 177.012 177.012
============================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
------------------------------------------------------------------------------------
data_out[0] clk (rising) NA 6.490 200.000 193.510
data_out[1] clk (rising) NA 6.490 200.000 193.510
data_out[2] clk (rising) NA 6.490 200.000 193.510
data_out[3] clk (rising) NA 6.490 200.000 193.510
data_out[4] clk (rising) NA 6.490 200.000 193.510
data_out[5] clk (rising) NA 6.490 200.000 193.510
data_out[6] clk (rising) NA 6.490 200.000 193.510
data_out[7] clk (rising) NA 6.490 200.000 193.510
dispout[0] clk (rising) NA 7.045 200.000 192.955
dispout[1] clk (rising) NA 7.045 200.000 192.955
dispout[2] clk (rising) NA 7.045 200.000 192.955
dispout[3] clk (rising) NA 7.045 200.000 192.955
dispout[4] clk (rising) NA 7.045 200.000 192.955
dispout[5] clk (rising) NA 7.045 200.000 192.955
dispout[6] clk (rising) NA 7.045 200.000 192.955
dispout[7] clk (rising) NA 7.045 200.000 192.955
dispout[8] clk (rising) NA 7.045 200.000 192.955
dispout[9] clk (rising) NA 7.045 200.000 192.955
dispout[10] clk (rising) NA 7.045 200.000 192.955
dispout[11] clk (rising) NA 7.045 200.000 192.955
dispout[12] clk (rising) NA 7.045 200.000 192.955
dispout[13] clk (rising) NA 7.045 200.000 192.955
ext_addr[0] clk (rising) NA 24.418 200.000 175.582
ext_addr[1] clk (rising) NA 26.403 200.000 173.597
ext_addr[2] clk (rising) NA 26.229 200.000 173.771
ext_addr[3] clk (rising) NA 27.203 200.000 172.797
ext_addr[4] clk (rising) NA 31.326 200.000 168.674
ext_addr[5] clk (rising) NA 31.800 200.000 168.201
ext_addr[6] clk (rising) NA 32.500 200.000 167.501
ext_addr[7] clk (rising) NA 35.796 200.000 164.205
ext_addr[8] clk (rising) NA 11.188 200.000 188.812
ext_addr[9] clk (rising) NA 11.188 200.000 188.812
ext_addr[10] clk (rising) NA 11.188 200.000 188.812
ext_addr[11] clk (rising) NA 11.188 200.000 188.812
ext_addr[12] clk (rising) NA 11.188 200.000 188.812
ext_addr[13] clk (rising) NA 11.188 200.000 188.812
ext_addr[14] clk (rising) NA 11.188 200.000 188.812
ext_addr[15] clk (rising) NA 11.188 200.000 188.812
int_act clk (rising) NA 6.538 200.000 193.462
p0_out[0] clk (rising) NA 6.490 200.000 193.510
p0_out[1] clk (rising) NA 6.490 200.000 193.510
p0_out[2] clk (rising) NA 6.490 200.000 193.510
p0_out[3] clk (rising) NA 6.490 200.000 193.510
p0_out[4] clk (rising) NA 6.490 200.000 193.510
p0_out[5] clk (rising) NA 6.490 200.000 193.510
p0_out[6] clk (rising) NA 6.490 200.000 193.510
p0_out[7] clk (rising) NA 6.490 200.000 193.510
p1_out[0] clk (rising) NA 6.490 200.000 193.510
p1_out[1] clk (rising) NA 6.490 200.000 193.510
p1_out[2] clk (rising) NA 6.490 200.000 193.510
p1_out[3] clk (rising) NA 6.490 200.000 193.510
p1_out[4] clk (rising) NA 6.490 200.000 193.510
p1_out[5] clk (rising) NA 6.490 200.000 193.510
p1_out[6] clk (rising) NA 6.490 200.000 193.510
p1_out[7] clk (rising) NA 6.490 200.000 193.510
p2_out[0] clk (rising) NA 6.490 200.000 193.510
p2_out[1] clk (rising) NA 6.490 200.000 193.510
p2_out[2] clk (rising) NA 6.490 200.000 193.510
p2_out[3] clk (rising) NA 6.490 200.000 193.510
p2_out[4] clk (rising) NA 6.490 200.000 193.510
p2_out[5] clk (rising) NA 6.490 200.000 193.510
p2_out[6] clk (rising) NA 6.490 200.000 193.510
p2_out[7] clk (rising) NA 6.490 200.000 193.510
p3_out[0] clk (rising) NA 6.490 200.000 193.510
p3_out[1] clk (rising) NA 6.490 200.000 193.510
p3_out[2] clk (rising) NA 6.490 200.000 193.510
p3_out[3] clk (rising) NA 6.490 200.000 193.510
p3_out[4] clk (rising) NA 6.490 200.000 193.510
p3_out[5] clk (rising) NA 6.490 200.000 193.510
p3_out[6] clk (rising) NA 6.490 200.000 193.510
p3_out[7] clk (rising) NA 6.490 200.000 193.510
sw1 System (rising) NA 6.468 200.000 193.532
sw2 System (rising) NA 6.468 200.000 193.532
sw3 System (rising) NA 6.468 200.000 193.532
sw4 System (rising) NA 8.014 200.000 191.986
====================================================================================
====================================
Detailed Report for Clock: clk
====================================
Starting Points with worst slack
********************************
Arrival
Instance Type Pin Net Time Slack
-------------------------------------------------------------------------------------------------
oc8051_top_1.oc8051_acc1.data_out[0] FDCE Q data_out_c[0] 2.159 164.205
oc8051_top_1.oc8051_acc1.data_out[2] FDCE Q data_out_c[2] 2.159 164.205
oc8051_top_1.oc8051_acc1.data_out[3] FDCE Q data_out_c[3] 2.159 164.205
oc8051_top_1.oc8051_acc1.data_out[4] FDCE Q data_out_c[4] 2.159 164.205
oc8051_top_1.oc8051_reg8_rd_ram.out[0] FDC Q rd_addr_r[0] 2.015 164.348
oc8051_top_1.oc8051_reg8_rd_ram.out[2] FDC Q rd_addr_r[2] 2.015 164.348
oc8051_top_1.oc8051_acc1.data_out[1] FDCE Q data_out_c[1] 2.159 164.506
oc8051_top_1.oc8051_acc1.data_out[5] FDCE Q data_out_c[5] 2.159 164.506
oc8051_top_1.oc8051_acc1.data_out[6] FDCE Q data_out_c[6] 2.159 164.506
oc8051_top_1.oc8051_acc1.data_out[7] FDCE Q data_out_c[7] 2.159 164.506
=================================================================================================
Ending Points with worst slack
******************************
Required
Instance Type Pin Net Time Slack
-----------------------------------------------------------------------------------------------------------------------
ext_addr[15:0] Port ext_addr[7] ext_addr[7] 200.000 164.205
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[0] rd_addr_m[0] 198.800 164.362
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[1] rd_addr_m[1] 198.800 164.362
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[2] rd_addr_m[2] 198.800 164.362
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 DIB[0] wr_data_m[0] 198.800 165.836
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 DIB[3] wr_data_m[3] 198.800 165.836
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 DIB[4] wr_data_m[4] 198.800 165.836
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 DIB[7] wr_data_m[7] 198.800 165.836
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[3] rd_addr_m[3] 198.800 166.052
oc8051_top_1.oc8051_ram_top1.oc8051_ram1.ram1 RAMB4_S8_S8 ADDRA[4] rd_addr_m[4] 198.800 166.052
=======================================================================================================================
Worst Paths Information
***********************
Path information for path number 1:
= Required time: 200.000
- Propagation time: 35.796
= Slack (critical) : 164.205
Starting point: oc8051_top_1.oc8051_acc1.data_out[0] / Q
Ending point: ext_addr[15:0] / ext_addr[7]
The start point is clocked by clk [rising] on pin C
The end point is clocked by clk [rising]
Instance / Net Pin Pin Arrival Fan
Name Type Name Dir Delay Time Out
----------------------------------------------------------------------------------------------------------------
oc8051_top_1.oc8051_acc1.data_out[0] FDCE Q Out 2.159 2.159
data_out_c[0] Net 10
oc8051_top_1.oc8051_ram_sel1.bit_out_2_3_0_am LUT3 I2 In 2.159
oc8051_top_1.oc8051_ram_sel1.bit_out_2_3_0_am LUT3 O Out 1.305 3.464
bit_out_2_3_0_am Net 1
oc8051_top_1.oc8051_ram_sel1.bit_out_2_3_0 MUXF5 I0 In 3.464
oc8051_top_1.oc8051_ram_sel1.bit_out_2_3_0 MUXF5 O Out 1.171 4.635
N_124 Net 1
oc8051_top_1.oc8051_ram_sel1.bit_out_2_0_bm LUT3 I2 In 4.635
oc8051_top_1.oc8051_ram_sel1.bit_out_2_0_bm LUT3 O Out 1.305 5.940
bit_out_2_0_bm Net 1
oc8051_top_1.oc8051_ram_sel1.bit_out_2_0 MUXF5 I1 In 5.940
oc8051_top_1.oc8051_ram_sel1.bit_out_2_0 MUXF5 O Out 0.870 6.809
N_59 Net 1
oc8051_top_1.oc8051_ram_sel1.bit_out_am.G_1 LUT4 I1 In 6.809
oc8051_top_1.oc8051_ram_sel1.bit_out_am.G_1 LUT4 O Out 1.305 8.114
G_1 Net 1
oc8051_top_1.oc8051_ram_sel1.bit_out MUXF5 I0 In 8.114
oc8051_top_1.oc8051_ram_sel1.bit_out MUXF5 O Out 1.076 9.191
bit_out Net 6
oc8051_top_1.oc8051_cy_select1.data_out_3_0 LUT4 I2 In 9.191
oc8051_top_1.oc8051_cy_select1.data_out_3_0 LUT4 O Out 1.305 10.496
alu_cy Net 19
oc8051_top_1.oc8051_cy_select1.alu_cy_i INV I In 10.496
oc8051_top_1.oc8051_cy_select1.alu_cy_i INV O Out 0.555 11.051
alu_cy_i Net 2
oc8051_top_1.oc8051_alu1.sub4_0_axb_0 LUT2 I0 In 11.051
oc8051_top_1.oc8051_alu1.sub4_0_axb_0 LUT2 O Out 1.690 12.741
sub4_0[0] Net 4
oc8051_top_1.oc8051_alu1.sub4_0_cry_0 MUXCY_L S In 12.741
oc8051_top_1.oc8051_alu1.sub4_0_cry_0 MUXCY_L LO Out 0.601 13.342
sub4_0_cry_0 Net 2
oc8051_top_1.oc8051_alu1.sub4_0_cry_1 MUXCY_L CI In 13.342
oc8051_top_1.oc8051_alu1.sub4_0_cry_1 MUXCY_L LO Out 0.100 13.442
sub4_0_cry_1 Net 2
oc8051_top_1.oc8051_alu1.sub4_0_cry_2 MUXCY_L CI In 13.442
oc8051_top_1.oc8051_alu1.sub4_0_cry_2 MUXCY_L LO Out 0.100 13.542
sub4_0_cry_2 Net 2
oc8051_top_1.oc8051_alu1.sub4_0_s_3 XORCY CI In 13.542
oc8051_top_1.oc8051_alu1.sub4_0_s_3 XORCY O Out 0.400 13.942
sub4_0[3] Net 2
oc8051_top_1.oc8051_alu1.sub4_2_axb_3_i_i LUT2 I0 In 13.942
oc8051_top_1.oc8051_alu1.sub4_2_axb_3_i_i LUT2 O Out 1.546 15.488
sub4_2_axb_3_i_i Net 2
oc8051_top_1.oc8051_alu1.sub4_2_cry_3 MUXCY_L S In 15.488
oc8051_top_1.oc8051_alu1.sub4_2_cry_3 MUXCY_L LO Out 0.504 15.992
sub4_2_cry_3 Net 1
oc8051_top_1.oc8051_alu1.sub4_2_s_4 XORCY CI In 15.992
oc8051_top_1.oc8051_alu1.sub4_2_s_4 XORCY O Out 0.785 16.777
sub4[4] Net 3
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